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Behavior Modification Wristwatch
A wristwatch including a watch band and a watch body having an octagon shaped perimeter and being red in color and having the word STOP thereon to resemble a stop sign.
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| Number | Title | Issue Date |
| 7981755 | Self aligned ring electrodes The present invention in one embodiment provides a method of manufacturing an electrode that includes providing at least one metal stud positioned in a via extending into a first dielectric layer, wherein an electrically conductive liner is positioned between at lea... | 07/19/2011 |
| 7943470 | Chip-stacked semiconductor device and manufacturing method thereof The semiconductor device according to the present invention includes a through electrode that penetrates through a silicon substrate, an isolation trench provided to penetrate through the silicon substrate to surround the through electrode, a silicon film in contact... | 05/17/2011 |
| 7910448 | Method for fabricating a mono-crystalline emitter Fabrication of a mono-crystalline emitter using a combination of selective and differential growth modes. The steps include providing a trench (14) formed on a silicon substrate (16) having opposed silicon oxide side walls (12); selectively grow... | 03/22/2011 |
| 7842579 | Method for manufacturing a semiconductor device having doped and undoped polysilicon layers Various illustrative embodiments of methods for manufacturing a semiconductor device are described. These methods may include, for example, forming a first polysilicon layer above a substrate, wherein the first polysilicon layer comprises a doped portion, and formin... | 11/30/2010 |
| 7790564 | Methods for fabricating active devices on a semiconductor-on-insulator substrate utilizing multiple depth shallow trench isolations Methods for fabricating a device structure in a semiconductor-on-insulator substrate. The method includes forming a first isolation region in the substrate device layer that extends from a top surface of the device layer to a first depth and forming a second isolati... | 09/07/2010 |
| 7727848 | Methods and semiconductor structures for latch-up suppression using a conductive region Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The semiconductor structure comprises first and second adjacent doped wells formed in the semiconductor material of a substrate. A trench, which includes a base and first sidewalls b... | 06/01/2010 |
| 7491618 | Methods and semiconductor structures for latch-up suppression using a conductive region Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The semiconductor structure comprises first and second adjacent doped wells formed in the semiconductor material of a substrate. A trench, which includes a base and first sidewalls b... | 02/17/2009 |
| 7432169 | Method for manufacturing semiconductor device An excessive etch in the conventional manufacturing process causes a roughened surface of a contact bottom, resulting in an increased variation in characteristics of semiconductor devices. A bipolar transistor having a collector region 4 provided in a bottom ... | 10/07/2008 |
| 7378326 | Printed circuit board with embedded capacitors therein and manufacturing process thereof A printed circuit board having embedded capacitors includes a double-sided copper-clad laminate including first circuit layers formed in the outer layers thereof, the first circuit layers including bottom electrodes and circuit patterns; dielectric layers formed by ... | 05/27/2008 |
| 7368334 | Silicon-on-insulator chip with multiple crystal orientations A silicon-on-insulator chip includes an insulator layer, typically formed over a substrate. A first silicon island with a surface of a first crystal orientation overlies the insulator layer and a second silicon island with a surface of a second crystal orientation a... | 05/06/2008 |
| 7354840 | Method for opto-electronic integration on a SOI substrate According to an exemplary embodiment, a method includes providing a silicon-on-insulator substrate including a buried oxide layer situated over a bulk silicon substrate and a silicon layer situated over the buried oxide layer. A trench is formed in the silicon layer... | 04/08/2008 |
| 7338848 | Method for opto-electronic integration on a SOI substrate and related structure According to an exemplary embodiment, a method includes providing a silicon-on-insulator substrate including a buried oxide layer situated over a bulk silicon substrate and a silicon layer situated over the buried oxide layer. A trench is formed in the silicon layer... | 03/04/2008 |
| 7329569 | Methods of forming semiconductor devices including mesa structures and multiple passivation layers A method of forming a semiconductor device may include forming a semiconductor structure on a substrate wherein the semiconductor structure defines a mesa having a mesa surface opposite the substrate and mesa sidewalls between the mesa surface and the substrate. A f... | 02/12/2008 |
| 7288827 | Self-aligned mask formed utilizing differential oxidation rates of materials A self-aligned oxide mask is formed utilizing differential oxidation rates of different materials. The self-aligned oxide mask is formed on a CVD grown base NPN base layer which compromises single crystal Si (or Si/SiGe) at active area and polycrystal Si (or Si/SiGe... | 10/30/2007 |
| 7268043 | Semiconductor device and method of manufacturing the same A semiconductor device and a method of manufacturing the same is disclosed. A trench is formed in an active region of a semiconductor substrate. A doped layer is formed on the inner walls of the trench. The trench is filled up with a first semiconductor layer. A gat... | 09/11/2007 |
| 7264978 | Field emission type cold cathode and method of manufacturing the cold cathode A field emission type cold cathode, comprising a substrate having a conductivity at least on the surface thereof, an insulation layer formed on the substate and having a first opening part, a gate electrode layer formed on the insulation layer, having a center gener... | 09/04/2007 |
| 7262089 | Methods of forming semiconductor structures The invention includes semiconductor structures having buried silicide-containing bitlines. Vertical surround gate transistor structures can be formed over the bitlines. The surround gate transistor structures can be incorporated into memory devices, such as, for ex... | 08/28/2007 |
| 7259069 | Semiconductor device and method of manufacturing the same A semiconductor device and a method of manufacturing the same is disclosed. A trench is formed in an active region of a semiconductor substrate. A doped layer is formed on the inner walls of the trench. The trench is filled up with a first semiconductor layer. A gat... | 08/21/2007 |
| 7232713 | Methods of forming interconnect lines In one aspect, the invention provides a method of forming an electrical connection in an integrated circuitry device. According to one preferred implementation, a diffusion region is formed in semiconductive material. A conductive line is formed which is laterally s... | 06/19/2007 |
| 7180159 | Bipolar transistor having base over buried insulating and polycrystalline regions A bipolar transistor in a monocrystalline semiconductor substrate (101), which has a first conductivity type and includes a surface layer (102) of the opposite conductivity type. The transistor comprises an emitter contact (110) on the surface l... | 02/20/2007 |
| 7176120 | Method of manufacturing semiconductor device A method of manufacturing a semiconductor device, including the steps of: forming first and second insulation films on a substrate; sequentially forming an organic sacrificing layer and first and second mask layers thereon; forming a wiring groove pattern in the sec... | 02/13/2007 |
| 7151035 | Semiconductor device and manufacturing method thereof A sidewall-insulation film 9 is provided on a side surface of a first opening portion 8a formed in a base extraction electrode 5B of a hetero-junction bipolar transistor, and a portion of the sidewall-insulation film 9 extends so a... | 12/19/2006 |
| 7135380 | Method for manufacturing semiconductor device In a conventional method for manufacturing a semiconductor device, there are problems that a concave part is formed in a formation region of an isolation region, no flat surface is formed in the isolation region, and a wiring layer is disconnected above the concave ... | 11/14/2006 |
| 7098113 | Method and system for providing a power lateral PNP transistor using a buried power buss A power lateral PNP device is disclosed which includes an epitaxial layer; a first and second collector region embedded in the epitaxial layer; an emitter region between the first and second collector regions. Therefore slots are placed in each of the regions. Accor... | 08/29/2006 |
| 7091085 | Reduced cell-to-cell shorting for memory arrays Bottom electrodes of memory cell capacitors are recessed to prevent electrical shorts between neighboring memory cells. A partially fabricated memory cell capacitor has a bottom electrode comprising titanium nitride (TiN) and hemispherical grained (HSG) silicon. The... | 08/15/2006 |
| 7042063 | Semiconductor wafer, semiconductor device, and process for manufacturing the semiconductor device A semiconductor wafer is disclosed in which a high concentration impurity layer is formed in a semiconductor wafer to a predetermined depth, in order to electrically connect electrodes formed on the principal face of the wafer without forming trenches and through ho... | 05/09/2006 |
| 7015115 | Method for forming deep trench isolation and related structure According to one embodiment, a structure comprises a substrate and a field oxide region, where the field oxide region has a top surface, and where the top surface of the field oxide region comprises substantially no cavities caused by lateral etching. The structure ... | 03/21/2006 |
| 7005359 | Bipolar junction transistor with improved extrinsic base region and method of fabrication A bipolar transistor and its fabrication are described. The extrinsic base region is formed by growing a second, more heavily doped, epitaxial layer over a first epitaxial layer. The second layer extends under, and is insulated from, an overlying polysilicon emitter... | 02/28/2006 |
| 7002190 | Method of collector formation in BiCMOS technology A heterobipolar transistor (HBT) for high-speed BiCMOS applications is provided in which the collector resistance, Rc, is lowered by providing a buried refractory metal silicide layer underneath the shallow trench isolation region on the subcollector of the device. ... | 02/21/2006 |
| 6995449 | Deep trench isolation region with reduced-size cavities in overlying field oxide According to an exemplary method for removing a hard mask in a deep trench isolation process, a hard mask is formed over the substrate, where the substrate includes at least one field oxide region. Thereafter, a trench is formed in the substrate, where the trench ha... | 02/07/2006 |
| 6979625 | Copper interconnects with metal capping layer and selective copper alloys High reliable copper interconnects are formed with copper or a low resistivity copper alloy filling relatively narrow openings and partially filling relatively wider openings and a copper alloy having improved electromigration resistance selectively deposited in the... | 12/27/2005 |
| 6977204 | Method for forming contact plug having double doping distribution in semiconductor device The present invention provides a method for forming a contact plug in a semiconductor device capable of preventing an increase of contact resistance caused by a decrease in dopant concentration and suppressing diffusions of dopants implanted into the contact. The do... | 12/20/2005 |
| 6974743 | Method of making encapsulated spacers in vertical pass gate DRAM and damascene logic gates Semiconductor devices having improved isolation are provided along with methods of fabricating such semiconductor devices. The improved isolation includes an encapsulated spacer formed within a gate region of a device. ... | 12/13/2005 |
| 6963108 | Recessed channel A memory cell with reduced short channel effects is described. A trench region is formed in a semiconductor substrate. A source region and a drain region are formed on opposing sides of the trench region, wherein a bottom of the source region and a bottom of the dra... | 11/08/2005 |
| 6955972 | Methods of fabricating integrated circuit devices having trench isolation structures Methods of fabricating integrated circuit devices include forming a trench in a face of an integrated circuit substrate. The trench has a trench sidewall and a trench floor. The method further including forming a first insulating layer on the trench sidewall that ex... | 10/18/2005 |
| 6946720 | Bipolar transistor for an integrated circuit having variable value emitter ballast resistors An integrated circuit including a bipolar transistor with improved forward second breakdown is disclosed. In one embodiment, the bipolar transistor includes a base, a collector, a plurality of emitter sections coupled to a common emitter and a ballast emitter for ea... | 09/20/2005 |
| 6936519 | Double polysilicon bipolar transistor and method of manufacture therefor A bipolar transistor, and manufacturing method therefor, with a substrate having a collector region and a base structure provided thereon. An emitter structure is formed over the base structure and an extrinsic base structure is formed over the base structure and ov... | 08/30/2005 |
| 6927112 | Radical processing of a sub-nanometer insulation film A method of nitriding an insulation film, includes the steps of forming nitrogen radicals by high-frequency plasma, and causing nitridation in a surface of an insulation film containing therein oxygen, by supplying the nitrogen radicals to the surface of the insulat... | 08/09/2005 |
| 6924023 | Method of manufacturing a structure having pores A method of manufacturing a nonostructure, which enables cylindrical pores arrayed according to any periodic pattern to be easily made on a substrate over a large area at a low cost in a short period of time. The method of manufacturing a structure having such pores... | 08/02/2005 |
| 6900105 | Semiconductor device and method of manufacture In a semiconductor manufacturing method, an emitter region (211) and a base enhancement region (207) are formed to provide linear voltage, capacitance and low resistance characteristics. In the manufacturing method, a semiconductor device (200) ... | 05/31/2005 |
