Class 438/360 - With epitaxial semiconductor formation in groove

Subclass of Class 438 - Semiconductor device manufacturing: process
Definition: Process for making a bipolar transistor additionally involving
No. of patents: 58
Last issue date: 05/15/2012

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Number	Title	Issue Date
8178415	Method for manufacturing RF powder A method for manufacturing RF powder wherein the RF powder is composed of a large amount of particles and used as collective RF powder (a powdery entity); and a large amount of RF powder particles can be obtained from a wafer in a stable manner and at a high yield i...	05/15/2012
7435656	Semiconductor device of transistor structure having strained semiconductor layer The semiconductor device comprises a p type Si substrate 10; a SiGe buffer layer 12 formed on the p type Si substrate 10 and having element isolation grooves 16 formed in the surface, which define an active region 18; a SiGe regrow...	10/14/2008
7368345	Flash memory devices and methods of fabricating the same Flash memory devices and methods of fabricating the same are disclosed. A disclosed method comprises doping at least one active region of a substrate, and forming an etching mask layer on the active region. The etching mask layer defines an opening exposing a portio...	05/06/2008
7354840	Method for opto-electronic integration on a SOI substrate According to an exemplary embodiment, a method includes providing a silicon-on-insulator substrate including a buried oxide layer situated over a bulk silicon substrate and a silicon layer situated over the buried oxide layer. A trench is formed in the silicon layer...	04/08/2008
7351633	Method of fabricating semiconductor device using selective epitaxial growth A method of fabricating a semiconductor device using selective epitaxial growth (SEG) is disclosed. The method comprises; forming a seed window exposing a portion of a substrate through an interlayer insulating layer, growing a single crystal silicon SEG layer in th...	04/01/2008
7339254	SOI substrate for integration of opto-electronics with SiGe BiCMOS According to an exemplary embodiment, a structure includes a silicon-on-insulator substrate including a buried oxide layer situated over a bulk silicon substrate and a silicon layer situated over the buried oxide layer. The structure further includes a trench formed...	03/04/2008
7338848	Method for opto-electronic integration on a SOI substrate and related structure According to an exemplary embodiment, a method includes providing a silicon-on-insulator substrate including a buried oxide layer situated over a bulk silicon substrate and a silicon layer situated over the buried oxide layer. A trench is formed in the silicon layer...	03/04/2008
7268043	Semiconductor device and method of manufacturing the same A semiconductor device and a method of manufacturing the same is disclosed. A trench is formed in an active region of a semiconductor substrate. A doped layer is formed on the inner walls of the trench. The trench is filled up with a first semiconductor layer. A gat...	09/11/2007
7259069	Semiconductor device and method of manufacturing the same A semiconductor device and a method of manufacturing the same is disclosed. A trench is formed in an active region of a semiconductor substrate. A doped layer is formed on the inner walls of the trench. The trench is filled up with a first semiconductor layer. A gat...	08/21/2007
7153731	Method of forming a field effect transistor with halo implant regions A method of forming a field effect transistor includes forming a channel region within bulk semiconductive material of a semiconductor substrate. Source/drain regions are formed on opposing sides of the channel region. An insulative dielectric region is formed withi...	12/26/2006
7151035	Semiconductor device and manufacturing method thereof A sidewall-insulation film 9 is provided on a side surface of a first opening portion 8a formed in a base extraction electrode 5B of a hetero-junction bipolar transistor, and a portion of the sidewall-insulation film 9 extends so a...	12/19/2006
6939773	Semiconductor devices and manufacturing methods thereof Semiconductor device fabrication methods include forming an oxide layer on a semiconductor substrate, forming an arrangement trench on the semiconductor substrate by patterning the oxide layer and the semiconductor substrate, forming a nitride layer on the arrangeme...	09/06/2005
6900105	Semiconductor device and method of manufacture In a semiconductor manufacturing method, an emitter region (211) and a base enhancement region (207) are formed to provide linear voltage, capacitance and low resistance characteristics. In the manufacturing method, a semiconductor device (200) ...	05/31/2005
6884687	SEMICONDUCTOR PROCESSING METHODS OF FORMING INTEGRATED CIRCUITRY, FORMING CONDUCTIVE LINES, FORMING A CONDUCTIVE GRID, FORMING A CONDUCTIVE NETWORK, FORMING AN ELECTRICAL INTERCONNECTION TO A NODE LOCATION, FORMING AN ELECTRICAL INTERCONNECTION WITH A TRANSISTOR SOURCE/DRAIN REGION, AND INTEGRATED CIRCUITRY In one aspect, the invention provides a method of forming an electrical connection in an integrated circuitry device. According to one preferred implementation, a diffusion region is formed in semiconductive material. A conductive line is formed which is laterally s...	04/26/2005
6861311	SEMICONDUCTOR PROCESSING METHODS OF FORMING INTEGRATED CIRCUITRY, FORMING CONDUCTIVE LINES, FORMING A CONDUCTIVE GRID, FORMING A CONDUCTIVE NETWORK, FORMING AN ELECTRICAL INTERCONNECTION TO A NODE LOCATION, FORMING AN ELECTRICAL INTERCONNECTION WITH A TRANSISTOR SOURCE/DRAIN REGION, AND INTEGRATED CIRCUITRY In one aspect, the invention provides a method of forming an electrical connection in an integrated circuitry device. According to one preferred implementation, a diffusion region is formed in semiconductive material. A conductive line is formed which is laterally s...	03/01/2005
6855612	Method for fabricating a bipolar transistor A method for producing bipolar transistors with the aid of selective epitaxy for producing a collector and base. The method includes widening the area of the base either by the isotropic etching of the conductive layer or by the oxidation of the conductive layer and...	02/15/2005
6815305	Method for fabricating BICMOS semiconductor devices A method for fabricating a semiconductor device is described in which isolation layers and a collector of a BJT are simultaneously formed by an epitaxtial growth process during a process of fabricating a BiCMOS. The method for fabricating a semiconductor device of t...	11/09/2004
6790697	Optical semiconductor device and method of fabricating the same An optical semiconductor device includes an optical semiconductor element, a semiconductor region, and a buried layer. The optical semiconductor element is formed on a semiconductor substrate. The semiconductor region opposes the optical semiconductor element and es...	09/14/2004
6740552	Method of making vertical diode structures A method of making a vertical diode is provided, the vertical dioxide having associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the d...	05/25/2004
6737688	Method for manufacturing semiconductor device The present invention discloses a method for manufacturing a semiconductor device. A device isolation film has a shape of an insulating spacer at an interface of active regions composed of a epitaxial silicon layer in a device isolation region of a semiconductor sub...	05/18/2004
6727157	Method for forming a shallow trench isolation using air gap In fabricating a shallow trench isolation (STI), a silicon oxide layer, a silicon nitride layer and a moat pattern is sequentially deposited on a silicon substrate. Next, the silicon nitride layer and the silicon oxide layer is etched using the moat pattern as a mas...	04/27/2004
6723618	Methods of forming field isolation structures Field isolation structures and methods of forming field isolation structures are described. In one implementation, the method includes etching a trench within a monocrystalline silicon substrate. The trench has sidewalls and a base, with the base comprising monocrys...	04/20/2004
6635543	SOI hybrid structure with selective epitaxial growth of silicon A method and structure for selectively growing epitaxial silicon in a trench formed within a silicon-on-insulator (SOI) structure. The SOI structure includes a buried oxide layer (BOX) on a bulk silicon substrate, and a silicon layer on the BOX. A pad lay...	10/21/2003
6599793	Memory array with salicide isolation The present invention provides a memory array fabricated by complementary metal-oxide-semiconductor salicide process. The memory array comprises a semiconductor substrate. Multitudes of first isolation devices are aligned in the semiconductor substrate an...	07/29/2003
6593200	Method of forming an integrated inductor and high speed interconnect in a planarized process with shallow trench isolation A method of forming a semiconductor device with an inductor and/or high speed interconnect. The method comprises forming an epitaxial layer over the substrate, forming an opening through the epitaxial layer to expose an underlying region of the substrate,...	07/15/2003
6579771	Self aligned compact bipolar junction transistor layout, and method of making same The invention relates to a process of forming a bipolar junction transistor (BJT) that includes forming a topology over a substrate. Thereafter, a spacer is formed at the topology. A base layer is formed from epitaxial silicon above the spacer and at the ...	06/17/2003
6569744	Method of converting a metal oxide semiconductor transistor into a bipolar transistor The present invention provides a method of manufacturing a bipolar transistor. The method includes producing an opening in a dielectric layer located over a substrate and forming a collector in the substrate by implanting a first dopant through the openin...	05/27/2003
6528379	Method for manufacturing semiconductor integrated circuit device A buried layer of a collector region and a buried layer of a collector taking-out region are formed at the same time at each epitaxial layer when the collector region and the collector taking-out region of the semiconductor integrated circuit device accor...	03/04/2003
6509242	Heterojunction bipolar transistor A heterojunction bipolar transistor includes an emitter or collector region of doped silicon, a base region including silicon-germanium, and a spacer. The emitter or collector region form a heterojunction with the base region. The spacer is positioned to ...	01/21/2003
6506657	Process for forming damascene-type isolation structure for BJT device formed in trench Isolation of a heterojunction bipolar transistor device in an integrated circuit is accomplished by forming the device within a trench in dielectric material overlying single crystal silicon. Precise control over the thickness of the initially-formed diel...	01/14/2003
6495421	Manufacture of semiconductor material and devices using that material A method is described of manufacturing a semiconductor material having a zone (200) with p-conductivity type and n-conductivity type regions with dopant concentrations and dimensions such that, when the n- and p-conductivity type regions are depleted of f...	12/17/2002
6326287	Semiconductor device and method of fabricating the same A semiconductor device comprising a semiconductor substrate including an electronic element such as a MOSFET, interlayer dielectric (silicon oxide layer or BPSG layer) formed on the semiconductor substrate, a through-hole formed in the interlayer dielectr...	12/04/2001
6261914	Process for improving local uniformity of chemical mechanical polishing using a self-aligned polish rate enhancement layer A method for making a semiconductor device, includes forming an oxide layer on a silicon substrate, forming a nitride layer over the oxide layer; depositing one of a doped oxide layer and an undoped porous oxide layer on the nitride layer, etching trenche...	07/17/2001
6258686	Manufacturing method of semiconductor device and semiconductor device A manufacturing method of a bipolar transistor that can reduce, without increasing capacitance between base-collector, withstand voltage deterioration and leakage between emitter-base is provided. On an upper surface of an active area of a semiconductor s...	07/10/2001
6211571	Method and apparatus for testing chips Method and apparatus for the testing of substrates which are provided with a wiring structure, in particular, chips (21), in conjunction with which, by means of a solder-deposit carrier (25) which is provided with a structured, electrically conductive coa...	04/03/2001
6130139	Method of manufacturing trench-isolated semiconductor device The top surface of a P-type semiconductor substrate is partitioned into an active region to be formed with an element and an isolation region surrounding the active region. The isolation region is composed of trench portions and dummy semiconductor portio...	10/10/2000
6057184	Semiconductor device fabrication method using connecting implants A semiconductor device and method of fabrication for such device in which a P- epitaxial layer is positioned above a P++ substrate. A P++ buried layer implant is positioned within the device between the P++ substrate and the P- epitaxial layer. A connecti...	05/02/2000
5904535	Method of fabricating a bipolar integrated structure A process for fabricating a bipolar transistor on a silicon-on-insulator substrate which includes etching a bipolar transistor area into the substrate, wherein the bipolar transistor area has substantially vertical sidewalls and a bottom, and forming a bu...	05/18/1999
5504018	Process of fabricating bipolar transistor having epitaxially grown base layer without deterioration of transistor characteristics A bipolar transistor has a base rink structure epitaxially grown from an overhang portion of a poly-crystal silicon base electrode and an epitaxial collector layer and an intrinsic base structure grown on a concave central portion of the base rink structu...	04/02/1996
5422299	Method of forming single crystalline electrical isolated wells A quasi-dielectrically isolated (QDI) bipolar structure using epitaxial lateral overgrowth (ELO) uses a combination of dielectric isolation (DI) and junction isolation (JI), providing better isolation properties than JI, while providing better heat dissip...	06/06/1995

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Class 438/360 - With epitaxial semiconductor formation in groove