Quotables
"To place a man in a multi-stage rocket and project him into the controlling gravitational field of the moon where the passengers can make scientific observations, perhaps land alive, and then return to earth--all that constitutes a wild dream worthy of Jules Verne. I am bold enough to say that such a man-made voyage will never occur regardless of all future advances."
Lee deForest, American radio pioneer ; 1957
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| Number | Title | Issue Date |
| 7968418 | Apparatus and method for isolating integrated circuit components using deep trench isolation and shallow trench isolation An isolation trench structure includes both a deep trench isolation (DTI) trench and a shallow trench isolation (STI) trench. The DTI trench can be formed by etching a deeper, narrower trench in a substrate and filling the deeper trench with one or more materials (s... | 06/28/2011 |
| 7429505 | Method of fabricating fin field effect transistor using isotropic etching technique Methods of fabricating a fin field effect transistor (FinFET) are disclosed. Embodiments of the invention provide methods of fabricating FinFETs by optimizing a method for forming the fin so that a short channel effect is prevented and high integration is achieved. ... | 09/30/2008 |
| 7396732 | Formation of deep trench airgaps and related applications A method for forming deep trench or via airgaps in a semiconductor substrate is disclosed comprising the steps of patterning a hole in the substrate, partly fill said hole with a sacrificial material (e.g. poly-Si), depositing spacers on the sidewalls of the unfille... | 07/08/2008 |
| 7393731 | Semiconductor device and method of manufacturing the same A silicon nitride film is formed between interlayer insulating films covering an upper surface of an element formed on a surface of a semiconductor layer. With this structure, a semiconductor device comprising an isolation insulating film of PTI structure, which sup... | 07/01/2008 |
| 7354812 | Multiple-depth STI trenches in integrated circuit fabrication Multiple trench depths within an integrated circuit device are formed by first forming trenches in a substrate to a first depth, but of varying widths. Formation of a dielectric layer can cause some of the trenches to fill or close off while leaving other, wider tre... | 04/08/2008 |
| 7348652 | Bulk-isolated PN diode and method of forming a bulk-isolated PN diode A technique for making a bulk isolated PN diode. Specifically, a technique is provided for making a voltage clamp with a pair of bulk isolated PN diode. Another embodiment provides for a voltage clamp with a pair of bulk isolated PN diodes in parallel with a pair of... | 03/25/2008 |
| 7344949 | Non-volatile memory device and method of fabricating the same A method of fabricating an a non-volatile memory includes forming trench isolation regions in an inactive region of a semiconductor substrate, adjacent trench isolation regions defining respective protrusions having rounded edges therebetween, wherein upper surfaces... | 03/18/2008 |
| 7304848 | Apparatus for performance testing of heat dissipating modules An apparatus (10) for performance testing of heat dissipating modules (19) includes an enclosure (11) configured for receiving the heat dissipating module therein, a vertically movable platform (13) for supporting the enclosure thereon, a... | 12/04/2007 |
| 7299537 | Method of making an integrated inductor An inductor comprises a substrate comprising a semiconductor material, a first dielectric layer over the substrate, a magnetic layer over the first dielectric layer, a second dielectric layer over the magnetic layer, and a conductor over the second dielectric layer.... | 11/27/2007 |
| 7279381 | Method for fabricating cell transistor of flash memory A method for fabricating a cell transistor of a flash memory including a device isolation film is disclosed, to prevent the mouse bite and the residue of a gate electrode, which includes the steps of forming a moat pattern of STI structure on a semiconductor substra... | 10/09/2007 |
| 7279376 | Method for manufacturing semiconductor device The present invention provides a technology for forming the trenches having different depths in one semiconductor substrate, which enables easily conducting the photo resist process employed for the etch process and forming trenches at higher depth dimension accurac... | 10/09/2007 |
| 7268413 | Bipolar transistors with low-resistance emitter contacts Many integrated circuits include a type of transistor known as a bipolar junction transistor, which has an emitter contact formed of polysilicon. Unfortunately, polysilicon has a relatively high electrical resistance that poses an obstacle to improving switching spe... | 09/11/2007 |
| 7265010 | High performance vertical PNP transistor method The invention includes a method and resulting structure for fabricating high performance vertical NPN and PNP transistors for use in BiCMOS devices. The resulting high performance vertical PNP transistor includes an emitter region including silicon and germanium, an... | 09/04/2007 |
| 7253020 | Deuterium alloy process for image sensors A method of alloying an image sensor is disclosed. The method comprises forming various semiconductor devices in a semiconductor substrate. Then, an insulator layer is formed over the semiconductor devices. Finally, deuterium gas is used to alloy said image sensor a... | 08/07/2007 |
| 7247534 | Silicon device on Si:C-OI and SGOI and method of manufacture A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a second material on the substrate. The first material and the second mat... | 07/24/2007 |
| 7232726 | Trench-gate semiconductor device and method of manufacturing Consistent with an example embodiment a trench-gate semiconductor device, for example a MOSFET or IGBT, having a field plate provided below the trenched gate is manufactured using a process with improved reproducibility. The process includes the steps of etching a f... | 06/19/2007 |
| 7224027 | High voltage power MOSFET having a voltage sustaining region that includes doped columns formed by trench etching and diffusion from regions of oppositely doped polysilicon A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a first or second conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an e... | 05/29/2007 |
| 7189614 | Method for fabricating a trench structure which is electrically connected to a substrate on one side via a buried contact A method for fabricating a trench structure, in particular a trench capacitor with an insulation collar, which is electrically connected to a substrate on one side via a buried contact. Fabrication includes, for example, providing a trench in the substrate using a h... | 03/13/2007 |
| 7179691 | Method for four direction low capacitance ESD protection The invention describes a structure and a process for providing ESD semiconductor protection with reduced input capacitance. The structure consists of heavily doped P+ guard rings surrounding the I/O ESD protection device and the Vcc to Vss protection device. In add... | 02/20/2007 |
| 7172914 | Method of making uniform oxide layer A method of forming a semiconductor structure includes forming an isolation region in a semiconductor substrate. A first oxide layer is on the substrate, a first sacrificial layer is on the first oxide layer, and a first nitride layer is on the first sacrificial lay... | 02/06/2007 |
| 7170126 | Structure of vertical strained silicon devices A trench capacitor vertical-transistor DRAM cell in a SiGe wafer compensates for overhang of the pad nitride by forming an epitaxial strained silicon layer on the trench walls that improves transistor mobility, removes voids from the poly trench fill and reduces res... | 01/30/2007 |
| 7169654 | Method of forming a semiconductor device A method of integrating a non-MOS transistor device and a CMOS electronic device on a semiconductor substrate includes forming openings within an active semiconductor layer in first and second regions of a semiconductor substrate. The first region corresponds to a n... | 01/30/2007 |
| 7163871 | Manufacturing method of semiconductor device and oxidization method of semiconductor substrate A manufacturing method of a semiconductor device having a trench is provided to form, at a corner portion of the trench, an oxide film which is greater in thickness and smaller in stress than at other portions. When the trench formed in the semiconductor substrate i... | 01/16/2007 |
| 7157324 | Transistor structure having reduced transistor leakage attributes Undesirable transistor leakage in transistor structures becomes greatly reduced in substrates having a doped implant region formed via pulling back first and second layers of a process stack. A portion of the substrate, which also has first and second layers deposit... | 01/02/2007 |
| 7153731 | Method of forming a field effect transistor with halo implant regions A method of forming a field effect transistor includes forming a channel region within bulk semiconductive material of a semiconductor substrate. Source/drain regions are formed on opposing sides of the channel region. An insulative dielectric region is formed withi... | 12/26/2006 |
| 7153733 | Method of fabricating fin field effect transistor using isotropic etching technique Methods of fabricating a fin field effect transistor (FinFET) are disclosed. Embodiments of the invention provide methods of fabricating FinFETs by optimizing a method for forming the fin so that a short channel effect is prevented and high integration is achieved. ... | 12/26/2006 |
| 7151035 | Semiconductor device and manufacturing method thereof A sidewall-insulation film 9 is provided on a side surface of a first opening portion 8a formed in a base extraction electrode 5B of a hetero-junction bipolar transistor, and a portion of the sidewall-insulation film 9 extends so a... | 12/19/2006 |
| 7149155 | Channeled dielectric re-recordable data storage medium A re-recordable data storage medium is disclosed. One embodiment of the medium includes a dielectric material and a filler material. The dielectric material is organized in columnar channels over which memory cells are logically distributed. The filler material is w... | 12/12/2006 |
| 7141478 | Multi-stage EPI process for forming semiconductor devices, and resulting device The present invention is generally directed to a multi-stage epi process for forming semiconductor devices, and the resulting device. In one illustrative embodiment, the method comprises forming a first layer of epitaxial silicon above a surface of a semiconducting ... | 11/28/2006 |
| 7135380 | Method for manufacturing semiconductor device In a conventional method for manufacturing a semiconductor device, there are problems that a concave part is formed in a formation region of an isolation region, no flat surface is formed in the isolation region, and a wiring layer is disconnected above the concave ... | 11/14/2006 |
| 7125780 | Dielectric isolation type semiconductor device and method for manufacturing the same A dielectric isolation type semiconductor device and a manufacturing method therefor achieve high dielectric resistance while preventing the dielectric strength of the semiconductor device from being limited depending on the thickness of a dielectric layer and the t... | 10/24/2006 |
| 7118981 | Method of fabricating an integrated silicon-germanium heterobipolar transistor and an integrated silicon-germanium heterobipolar transistor In a method of fabricating an integrated silicon-germanium heterobipolar transistor a silicon dioxide layer arranged between a silicon-germanium base layer and a silicon emitter layer is formed by means of Rapid Thermal Processing (RTP) to ensure enhanced component ... | 10/10/2006 |
| 7087498 | Method for controlling trench depth in shallow trench isolation features A method for forming a trench in a semiconductor silicon substrate. An anti-reflective coating layer and a photoresist layer are formed over the substrate and patterned in accordance with a location for the trench. During the trench etch into the silicon substrate, ... | 08/08/2006 |
| 7087472 | Method of making a vertical compound semiconductor field effect transistor device In one embodiment, a method for fabricating a compound semiconductor vertical FET device includes forming a first trench in a body of semiconductor material, and forming a self-aligned second trench within the first trench to define a channel region. A doped gate re... | 08/08/2006 |
| 7084455 | Power semiconductor device having a voltage sustaining region that includes terraced trench with continuous doped columns formed in an epitaxial layer A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a first conductivity type and forming a voltage sustaining region on the substrate. The voltage sustaining region is formed in the following manner. First, a... | 08/01/2006 |
| 7071073 | Process for manufacturing low-cost and high-quality SOI substrates For manufacturing an SOI substrate, the following steps are carried out: providing a wafer of semiconductor material; forming, inside the wafer, a plurality of passages forming a labyrinthine cavity and laterally delimiting a plurality of pillars of semiconductor ma... | 07/04/2006 |
| 7037798 | Bipolar transistor structure with self-aligned raised extrinsic base and methods The invention includes methods of fabricating a bipolar transistor that adds a silicon germanium (SiGe) layer or a third insulator layer of, e.g., high pressure oxide (HIPOX), atop an emitter cap adjacent the intrinsic base prior to forming a link-up layer. This add... | 05/02/2006 |
| 7029723 | Forming chemical vapor depositable low dielectric constant layers Carborane may be used as a precursor to form low dielectric constant dielectrics. The carborane material may be modified to enable it to be deposited by chemical vapor deposition. ... | 04/18/2006 |
| 7026666 | Self-aligned NPN transistor with raised extrinsic base A self-aligned bipolar transistor and a method of formation thereof are provided. The bipolar transistor has a raised extrinsic base such that the link base resistance is reduced by providing an extrinsic base which is thicker than the intrinsic base. The increase i... | 04/11/2006 |
| 6998324 | Methods of fabricating silicon on insulator substrates for use in semiconductor devices Example methods of fabricating a silicon on insulator substrate are disclosed. One example method may include forming a plurality of trenches on a substrate, forming an insulation layer on the trenches, removing a portion of the insulation layer formed on the trench... | 02/14/2006 |
