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| Number | Title | Issue Date |
| 7799652 | Method for producing epitaxial wafer with buried diffusion layer and epitaxial wafer with buried diffusion layer There is disclosed a method for producing an epitaxial wafer with a buried diffusion layer comprising: implanting an impurity into a silicon single crystal wafer; subsequently diffusing the impurity in the wafer to... | 09/21/2010 |
| 7384802 | ESD protection device for high voltage An electrostatic discharge (ESD) protection structure and a method for forming the same are provided. The structure includes a substrate having a buried layer, and a first and a second high-voltage well region on the buried layer. The first and second high-voltage w... | 06/10/2008 |
| 7381623 | Pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performance The embodiments of the invention provide a method, etc. for a pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performance. More specifically, one method begins by forming a first gate and a second ga... | 06/03/2008 |
| 7371650 | Method for producing a transistor structure A method for fabricating a transistor structure with a first and a second bipolar transistor having different collector widths is presented. The method includes providing a semiconductor substrate, introducing a first buried layer of the first bipolar transistor and... | 05/13/2008 |
| 7332408 | Isolation trenches for memory devices Methods and apparatus are provided. A first dielectric plug is formed in a portion of a trench that extends into a substrate of a memory device so that an upper surface of the first dielectric plug is recessed below an upper surface of the substrate. The first diele... | 02/19/2008 |
| 7320922 | Integrated circuit and method for manufacturing an integrated circuit on a semiconductor chip An integrated circuit on a semiconductor chip is provided with a first bipolar transistor and a second bipolar transistor. The first bipolar transistor has a first collector region of a first conductivity type, grown by at least one epitaxial layer, and the second b... | 01/22/2008 |
| 7273815 | Etch features with reduced line edge roughness A method for forming a feature in a layer with reduced line edge roughening is provided. A photoresist layer is formed over the layer. The photoresist layer is patterned to form photoresist features with photoresist sidewalls. A sidewall layer with a thickness less ... | 09/25/2007 |
| 7268043 | Semiconductor device and method of manufacturing the same A semiconductor device and a method of manufacturing the same is disclosed. A trench is formed in an active region of a semiconductor substrate. A doped layer is formed on the inner walls of the trench. The trench is filled up with a first semiconductor layer. A gat... | 09/11/2007 |
| 7259069 | Semiconductor device and method of manufacturing the same A semiconductor device and a method of manufacturing the same is disclosed. A trench is formed in an active region of a semiconductor substrate. A doped layer is formed on the inner walls of the trench. The trench is filled up with a first semiconductor layer. A gat... | 08/21/2007 |
| 7195994 | Method for production of deep p regions in silicon, and semiconductor components produced using the method The invention relates to a method for production of deep p regions in silicon, with the method having the following step: bombardment of an n substrate section, an n epitaxial section or an exposed weakly doped n region of a semiconductor component that is to be pro... | 03/27/2007 |
| 7195985 | CMOS transistor junction regions formed by a CVD etching and deposition sequence This invention adds to the art of replacement source-drain cMOS transistors. Processes may involve etching a recess in the substrate material using one equipment set, then performing deposition in another. Disclosed is a method to perform the etch and subsequent dep... | 03/27/2007 |
| 7151035 | Semiconductor device and manufacturing method thereof A sidewall-insulation film 9 is provided on a side surface of a first opening portion 8a formed in a base extraction electrode 5B of a hetero-junction bipolar transistor, and a portion of the sidewall-insulation film 9 extends so a... | 12/19/2006 |
| 7141484 | Electrostatic discharge protection circuit of non-gated diode and fabrication method thereof A non-gated diode structure of a silicon-on-insulator, having a silicon-on-insulator substrate, a pair of isolating structures, a first type doped region and a second type doped region. The silicon-on-insulation substrate has a stack of a substrate, an insulation la... | 11/28/2006 |
| 7135364 | Method of fabricating semiconductor integrated circuit The lateral pnp transistor encompasses a p-type semiconductor substrate, an n-type first buried region disposed on the semiconductor substrate, an n-type uniform base region disposed on the first buried region, an n-type first plug region disposed in the uniform bas... | 11/14/2006 |
| 7118981 | Method of fabricating an integrated silicon-germanium heterobipolar transistor and an integrated silicon-germanium heterobipolar transistor In a method of fabricating an integrated silicon-germanium heterobipolar transistor a silicon dioxide layer arranged between a silicon-germanium base layer and a silicon emitter layer is formed by means of Rapid Thermal Processing (RTP) to ensure enhanced component ... | 10/10/2006 |
| 7060583 | Method for manufacturing a bipolar transistor having a polysilicon emitter In the inventive method for manufacturing a bipolar transistor having a polysilicon emitter, a collector region of a first conductivity type and, adjoining thereto, a basis region of a second conductivity type will be generated at first. At least one layer of an ins... | 06/13/2006 |
| 7037798 | Bipolar transistor structure with self-aligned raised extrinsic base and methods The invention includes methods of fabricating a bipolar transistor that adds a silicon germanium (SiGe) layer or a third insulator layer of, e.g., high pressure oxide (HIPOX), atop an emitter cap adjacent the intrinsic base prior to forming a link-up layer. This add... | 05/02/2006 |
| 7027893 | Robotic tool coupler rapid-connect bus A tool changer comprising a master module and a tool module includes a rapid-connect communication bus between the master and tool modules. A unique tool identification number, along with other tool-related information, may be transmitted from the tool module to the... | 04/11/2006 |
| 6995068 | Double-implant high performance varactor and method for manufacturing same A varactor designed to enable voltage controlled oscillator (VCO) integration in wireless systems is the base-emitter junction of a specially optimized NPN device formed with a double base implant. A first, shallow implant optimizes capacitance, leakage current, and... | 02/07/2006 |
| 6977426 | Semiconductor device including high speed transistors and high voltage transistors disposed on a single substrate In a semiconductor device comprising a first bipolar transistor and a second bipolar transistor having different voltages formed on a semiconductor substrate made by forming an epitaxial layer on a silicon substrate, in an upper part of the silicon substrate the fir... | 12/20/2005 |
| 6939773 | Semiconductor devices and manufacturing methods thereof Semiconductor device fabrication methods include forming an oxide layer on a semiconductor substrate, forming an arrangement trench on the semiconductor substrate by patterning the oxide layer and the semiconductor substrate, forming a nitride layer on the arrangeme... | 09/06/2005 |
| 6927115 | Method of fabricating semiconductor integrated circuit The lateral pnp transistor encompasses a p-type semiconductor substrate, an n-type first buried region disposed on the semiconductor substrate, an n-type uniform base region disposed on the first buried region, an n-type first plug region disposed in the uniform bas... | 08/09/2005 |
| 6919253 | Method of forming a semiconductor device including simultaneously forming a single crystalline epitaxial layer and a polycrystalline or amorphous layer A method of fabricating a semiconductor device according to the present invention includes a step A of forming a polycrystalline or amorphous preliminary semiconductor layer on a surface of a substrate so as to have an opening portion and a step B of simultaneously ... | 07/19/2005 |
| 6900105 | Semiconductor device and method of manufacture In a semiconductor manufacturing method, an emitter region (211) and a base enhancement region (207) are formed to provide linear voltage, capacitance and low resistance characteristics. In the manufacturing method, a semiconductor device (200) ... | 05/31/2005 |
| 6893934 | Bipolar transistor device having phosphorous A Si1-xGex layer 111b functioning as the base composed of an i—Si1-xGex layer and a p+ Si1-xGex layer is formed on a collector layer 102, and a Si cap layer 111 | 05/17/2005 |
| 6881641 | Semiconductor device having a retrograde dopant profile in a channel region and method for fabricating the same An epitaxially grown channel layer is provided on a well structure after ion implantation steps and heat treatment steps are performed to establish a required dopant profile in the well structure. The channel layer may be undoped or slightly doped, as required, so t... | 04/19/2005 |
| 6815801 | Vertical bipolar transistor and a method of manufacture therefor including two epitaxial layers and a buried layer The present invention provides a vertical bipolar transistor 110, a method of manufacture therefor, and an integrated circuit including the same. The vertical bipolar transistor 110 may include, in one embodiment, a second epitaxial layer 140 lo... | 11/09/2004 |
| 6806158 | Mixed crystal layer growing method and device, and semiconductor device When a silicon-germanium mixed crystal layer is grown on a substrate by introducing a silicon source gas, a germanium source gas, a boron source gas, and a carbon source gas into a reaction chamber, the flow rate of the carbon source gas is set at 5 sccm or higher a... | 10/19/2004 |
| 6780725 | METHOD FOR FORMING A SEMICONDUCTOR DEVICE INCLUDING FORMING VERTICAL NPN AND PNP TRANSISTORS BY EXPOSING THE EPITAXIAL LAYER, FORMING A MONOCRYSTAL LAYER AND ADJUSTING THE IMPURITY CONCENTRATION IN THE EPITAXIAL LAYER A method of manufacturing vertical NPN and PNP transistors on a substrate includes forming a first oxide film, a P-polycrystal silicon film, and a second oxide film successively on N-silicon epitaxial film on the substrate. An opening is made in the first oxide film... | 08/24/2004 |
| 6767798 | Method of forming self-aligned NPN transistor with raised extrinsic base A self-aligned bipolar transistor and a method of formation thereof are provided. The bipolar transistor has a raised extrinsic base such that the link base resistance is reduced by providing an extrinsic base which is thicker than the intrinsic base. The increase i... | 07/27/2004 |
| 6756273 | Semiconductor component and method of manufacturing A semiconductor component includes a semiconductor layer (110) having a trench (326). The trench has first and second sides. A portion (713) of the semiconductor layer has a conductivity type and a charge density. The semiconductor component als... | 06/29/2004 |
| 6693344 | Semiconductor device having low and high breakdown voltage transistors A base of a low breakdown voltage npn bipolar transistor has p+ diffusion layers. A field insulating layer is formed on the p+ diffusion layer located between the p+ diffusion layer and an emitter, while the p+ ... | 02/17/2004 |
| 6649482 | Bipolar transistor with a silicon germanium base and an ultra small self-aligned polysilicon emitter and method of forming the transistor A low-power bipolar transistor is formed to have a silicon germanium base region, an intrinsic emitter region with a sub-lithographic width, and an oxide layer that is self aligned to an overlying extrinsic emitter. The silicon germanium base region incre... | 11/18/2003 |
| 6627515 | Method of fabricating a non-floating body device with enhanced performance A method of forming a buried silicon oxide region in a semiconductor substrate with portions of the buried silicon oxide region formed underlying portions of a strained silicon shape, and where the strained silicon shape is used to accommodate a semicondu... | 09/30/2003 |
| 6607960 | Bipolar transistor manufacturing method A method of manufacturing a bipolar transistor in a P-type substrate, including the steps of forming in the substrate a first N-type area; forming by epitaxy a first silicon layer; forming in this first layer, and substantially above the first area a seco... | 08/19/2003 |
| 6593199 | Method of manufacturing a semiconductor component and semiconductor component thereof A method of manufacturing a semiconductor component includes providing a substrate (110) having a first doping concentration and growing an epitaxial layer (120, 520) over the substrate. The epitaxial layer has a second doping concentration lower than the... | 07/15/2003 |
| 6579752 | Phosphorus dopant control in low-temperature Si and SiGe epitaxy A method of manufacturing a semiconductor device comprising the step of epitaxially growing of an n-type doped layer of a semiconductor material using an n-type dopant gas, the growth process being performed at a pressure higher than 2.66×104 ... | 06/17/2003 |
| 6541345 | Semiconductor device with SOI structure Disclosed is a semiconductor device including a SOI substrate having a SOI layer, in which a structure made from a semiconductor device is buried; a thick oxide film formed on the structure by selectively oxidizing the structure using as a mask an oxidati... | 04/01/2003 |
| 6518139 | Power semiconductor device structure with vertical PNP transistor A power semiconductor device structure formed in a chip of semiconductor material includes an N-type substrate and an N-type epitaxial layer. The structure comprises a P-type insulation region which forms a pocket in which control circuitry is formed, and... | 02/11/2003 |
| 6506657 | Process for forming damascene-type isolation structure for BJT device formed in trench Isolation of a heterojunction bipolar transistor device in an integrated circuit is accomplished by forming the device within a trench in dielectric material overlying single crystal silicon. Precise control over the thickness of the initially-formed diel... | 01/14/2003 |
