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| Number | Title | Issue Date |
| 8071454 | Method for manufacturing dielectric isolation type semiconductor device A method for manufacturing a dielectric isolation type semiconductor device comprises: forming a plurality of trenches in a first region on a major surface of a semiconductor substrate; forming a first dielectric layer on the major surface of the semiconductor subst... | 12/06/2011 |
| 8012842 | Method for fabricating isolated integrated semiconductor structures An integrated semiconductor structure that has first and second bipolar transistor structures. The first bipolar transistor structure has a doped tank region in contact with a doped tank region located underneath a contacting sinker. The second bipolar transistor st... | 09/06/2011 |
| 7393731 | Semiconductor device and method of manufacturing the same A silicon nitride film is formed between interlayer insulating films covering an upper surface of an element formed on a surface of a semiconductor layer. With this structure, a semiconductor device comprising an isolation insulating film of PTI structure, which sup... | 07/01/2008 |
| 7371650 | Method for producing a transistor structure A method for fabricating a transistor structure with a first and a second bipolar transistor having different collector widths is presented. The method includes providing a semiconductor substrate, introducing a first buried layer of the first bipolar transistor and... | 05/13/2008 |
| 7364957 | Method and apparatus for semiconductor device with improved source/drain junctions A semiconductor device with improved source/drain junctions and methods for fabricating the device are disclosed. A preferred embodiment comprises a MOS transistor with a gate structure overlying a substrate, lightly doped source/drain regions formed in the substrat... | 04/29/2008 |
| 7354812 | Multiple-depth STI trenches in integrated circuit fabrication Multiple trench depths within an integrated circuit device are formed by first forming trenches in a substrate to a first depth, but of varying widths. Formation of a dielectric layer can cause some of the trenches to fill or close off while leaving other, wider tre... | 04/08/2008 |
| 7265011 | Method of manufacturing a transistor A method of manufacturing a transistor according to some embodiments includes sequentially forming a dummy gate oxide layer and a dummy gate electrode on an active region of a semiconductor substrate, ion-implanting a first conductive impurity into source/drain regi... | 09/04/2007 |
| 7256433 | Bipolar transistor and a method of manufacturing the same A bipolar transistor having enhanced characteristics is fabricated by etching a base mesa, which is formed below an emitter mesa (upper emitter layer) and a base electrode, so as to have jut regions on the edges of its generally rectangular region. A mask film, e.g.... | 08/14/2007 |
| 7205631 | Poly-silicon stringer fuse A polysilicon silicide stringer fuse is constructed having a narrow width by using an overlay tolerance of the photo stepper tool instead of the minimum critical dimension tolerance of the stepper tool. In an example embodiment, a fuse (200) for integration w... | 04/17/2007 |
| 7196394 | Method and apparatus for a deposited fill layer A method of forming a semiconducting wafer is provided that utilizes fewer processing operations, reduces process variation, and lowers cost as well as production time. The method provided further improves via reliability by permitting vias to be formed with consist... | 03/27/2007 |
| 7172914 | Method of making uniform oxide layer A method of forming a semiconductor structure includes forming an isolation region in a semiconductor substrate. A first oxide layer is on the substrate, a first sacrificial layer is on the first oxide layer, and a first nitride layer is on the first sacrificial lay... | 02/06/2007 |
| 7135364 | Method of fabricating semiconductor integrated circuit The lateral pnp transistor encompasses a p-type semiconductor substrate, an n-type first buried region disposed on the semiconductor substrate, an n-type uniform base region disposed on the first buried region, an n-type first plug region disposed in the uniform bas... | 11/14/2006 |
| 7125780 | Dielectric isolation type semiconductor device and method for manufacturing the same A dielectric isolation type semiconductor device and a manufacturing method therefor achieve high dielectric resistance while preventing the dielectric strength of the semiconductor device from being limited depending on the thickness of a dielectric layer and the t... | 10/24/2006 |
| 7122431 | Methods of fabrication metal oxide semiconductor (MOS) transistors having buffer regions below source and drain regions Methods of forming a unit cell of a metal oxide semiconductor (MOS) transistor are provided. An integrated circuit substrate is formed. A MOS transistor is formed on the integrated circuit substrate. The MOS transistor has a source region, a drain region and a gate.... | 10/17/2006 |
| 7078312 | Method for controlling etch process repeatability Plasma etch processes incorporating etch chemistries which include hydrogen. In particular, high density plasma chemical vapor deposition-etch-deposition processes incorporating etch chemistries which include hydrogen that can effectively fill high aspect ratio (typ... | 07/18/2006 |
| 7049677 | Low cost dielectric isolation method for integration of vertical power MOSFET and lateral driver devices A semiconductor device has a driver device (10) in proximity to a power device (12). In making the semiconductor device, an N+ layer (24) is formed on a substrate (22). A portion of the N+ layer is removed, substantially down to the subst... | 05/23/2006 |
| 7045865 | Semiconductor device with resistor elements formed on insulating film A semiconductor device of the invention has a plurality of resistor elements formed on an element isolating oxide film in predetermined regions on a surface of a semiconductor substrate. Active regions are furnished close to the resistor elements. This allows the el... | 05/16/2006 |
| 7012319 | System for integrating a circuit on an isolation layer and method thereof A method for integrating a system on an isolation layer. A first isolation substrate including a first circuit deposition region and a first substrate-combining region, and a second isolation substrate including a second circuit deposition region and a second substr... | 03/14/2006 |
| 7008851 | Silicon-germanium mesa transistor A method in the fabrication of a silicon-germanium mesa transistor in a semiconductor process flow comprises the steps of providing a p-type doped silicon bulk substrate (10) having an n+-type doped surface region (31) being a subcollector; ... | 03/07/2006 |
| 6991982 | Method of manufacturing a semiconductor non-volatile memory A method of manufacturing a semiconductor device comprising a non-volatile memory with memory transistors and selection transistors. In this method a semiconductor body is provided with strip-shaped active regions (4) which are mutually isolated by field-oxid... | 01/31/2006 |
| 6979627 | Isolation trench A process for forming an isolation trench in a wafer. The process includes depositing (e.g. by a directional deposition process) a first dielectric material in the trench and then depositing a second dielectric material (e.g. by a directional deposition process) ove... | 12/27/2005 |
| 6964907 | Method of etching a lateral trench under an extrinsic base and improved bipolar transistor In a BJT, the extrinsic base to collector capacitance is reduced by forming a lateral trench between the extrinsic base region and collector. This is typically done by using an anisotropic wet etch process in a direction of a orientation wafer. ... | 11/15/2005 |
| 6962842 | Method of removing a sacrificial emitter feature in a BICMOS process with a super self-aligned BJT A method of removing a sacrificial emitter feature in a bipolar complementary metal oxide semiconductor (BICMOS) process with a super self-aligned bipolar junction transistor (BJT) is disclosed. According to the new method, a mask layer, such as an oxide deposited u... | 11/08/2005 |
| 6955957 | Method of forming a floating gate in a flash memory device Disclosed is a method of forming the floating gate in the flash memory device. After the first polysilicon film is deposited on the semiconductor substrate, the trench is formed on the first polysilicon film with the pad nitride film not deposited. The HDP oxide fil... | 10/18/2005 |
| 6949438 | Method of fabricating a bipolar junction transistor A substrate with a plurality of isolation structures for defining at least an active area thereon is provided. Ions of a first conductive type are implanted into the substrate to form a doping region in the active area. Following that, a protective layer is formed o... | 09/27/2005 |
| 6943088 | Method of manufacturing a trench isolation structure for a semiconductor device with a different degree of corner rounding In a trench isolation structure of a semiconductor device, oxide liners are formed within the trenches, wherein a non-oxidizable mask is employed during various oxidation steps, thereby creating different types of liner oxides and thus different types of corner roun... | 09/13/2005 |
| 6927112 | Radical processing of a sub-nanometer insulation film A method of nitriding an insulation film, includes the steps of forming nitrogen radicals by high-frequency plasma, and causing nitridation in a surface of an insulation film containing therein oxygen, by supplying the nitrogen radicals to the surface of the insulat... | 08/09/2005 |
| 6927115 | Method of fabricating semiconductor integrated circuit The lateral pnp transistor encompasses a p-type semiconductor substrate, an n-type first buried region disposed on the semiconductor substrate, an n-type uniform base region disposed on the first buried region, an n-type first plug region disposed in the uniform bas... | 08/09/2005 |
| 6911716 | Bipolar transistors with vertical structures A method for fabricating a bipolar transistor includes forming a vertical sequence of semiconductor layers, forming an implant mask on the last formed semiconductor layer, and implanting dopant ions into a portion of one or more of the semiconductor layers. The sequ... | 06/28/2005 |
| 6908831 | Method for fabricating a semiconductor structure with an encapsulation of a filling which is used for filling trenches A method for encapsulating a filling in a trench of a semiconductor substrate includes providing a first barrier layer in a trench and a second barrier layer disposed above the first barrier layer. The trench is filled with a filling, which is subsequently etched ba... | 06/21/2005 |
| 6909163 | High-frequency oscillator for an integrated semiconductor circuit and the use thereof A high frequency oscillator for an integrated semiconductor circuit is a component of the semiconductor circuit, which is comprised of a first silicon layer, an adjoining silicon dioxide layer (insulation layer), and an additional subsequent silicon layer (structure... | 06/21/2005 |
| 6908821 | Apparatus for adjusting input capacitance of semiconductor device and fabricating method An apparatus for finely adjusting the input capacitance of a semiconductor device and a method of fabricating the apparatus are disclosed. The invention adjusts finely the input capacitance without increasing a layout area of the device by using a capacitor construc... | 06/21/2005 |
| 6902975 | Non-volatile memory technology compatible with 1T-RAM process Methods of fabricating memory devices having non-volatile and volatile memory are provided. A substrate is provided, wherein the substrate has a non-volatile memory region and a volatile memory region. The non-volatile memory region has a storage device, such as a s... | 06/07/2005 |
| 6902971 | Transistor sidewall spacer stress modulation A semiconductor fabrication process and the resulting integrated circuit include forming a gate electrode (116) over a gate dielectric (104) over a semiconductor substrate (102). A spacer film (124) exhibiting a tensile stress characteris... | 06/07/2005 |
| 6900105 | Semiconductor device and method of manufacture In a semiconductor manufacturing method, an emitter region (211) and a base enhancement region (207) are formed to provide linear voltage, capacitance and low resistance characteristics. In the manufacturing method, a semiconductor device (200) ... | 05/31/2005 |
| 6876054 | Integrable DC/AC voltage transformer/isolator and ultra-large-scale circuit incorporating the same An electronic device, a method of manufacturing an electronic device and an integrated circuit that employs at least one such electronic device to couple first and second circuits together in an isolated fashion. In one embodiment, the electronic device includes a f... | 04/05/2005 |
| 6872447 | Surface-protective pressure-sensitive adhesive sheet The pressure-sensitive adhesive sheet for surface protection has a three-layered film formed by laminating a layer A, a layer B and a layer C in this order and a pressure-sensitive adhesive layer formed on the layer C; wherein the layer A contains a polyethylene in ... | 03/29/2005 |
| 6830988 | Method of forming an isolation structure for an integrated circuit utilizing grown and deposited oxide An isolation structure having both deep and shallow components is formed in a semiconductor workpiece by etching the workpiece to define raised precursor active device regions separated by sunken precursor isolation regions. An oxidation mask is patterned to expose ... | 12/14/2004 |
| 6830977 | METHODS OF FORMING AN ISOLATION TRENCH IN A SEMICONDUCTOR, METHODS OF FORMING AN ISOLATION TRENCH IN A SURFACE OF A SILICON WAFER, METHODS OF FORMING AN ISOLATION TRENCH-ISOLATED TRANSISTOR, TRENCH-ISOLATED TRANSISTOR, TRENCH ISOLATION STRUCTURES FORMED IN A SEMICONDUCTOR, MEMORY CELLS AND DRAMS A method of forming an isolation trench in a semiconductor includes forming a first isolation trench portion having a first depth and having a first sidewall intersecting a surface of the semiconductor at a first angle. The method also includes forming a second isol... | 12/14/2004 |
| 6822325 | Isolating temperature sensitive components from heat sources in integrated circuits Temperature sensitive devices may be shielded from temperature generating devices on the same integrated circuit by appropriately providing a trench that thermally isolates the heat generating devices from the temperature sensitive devices. In one embodiment, the tr... | 11/23/2004 |
