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| Number | Title | Issue Date |
| 7557010 | Method to improve writer leakage in a SiGe bipolar device The invention, in one aspect, provides a method for fabricating a semiconductor device, which includes conducting an etch through an opening in an emitter layer to form a cavity from an underlying oxide layer that exposes a doped tub. A first silicon/germanium (SiGe... | 07/07/2009 |
| 7422951 | Method of fabricating self-aligned bipolar transistor The present invention provides a method of fabricating a self-aligned bipolar transistor, by which the fabricating method can be simplified by forming P+ and N+ junctions by self-alignment and by which device reliability can be enhanced. The present invention includ... | 09/09/2008 |
| 7390721 | Methods of base formation in a BiCMOS process Methods for fabricating a heterojunction bipolar transistor having a raised extrinsic base is provided in which the base resistance is reduced by forming a silicide atop the raised extrinsic base that extends to the emitter region in a self-aligned manner. The silic... | 06/24/2008 |
| 7368764 | Heterojunction bipolar transistor and method to make a heterojunction bipolar transistor A heterojunction bipolar transistor and a method of making a heterojunction bipolar transistor. The heterojunction bipolar transistor includes: a regrown emitter region; an intrinsic base region forming a junction with the regrown emitter region; and an extrinsic ba... | 05/06/2008 |
| 7354820 | Heterojunction bipolar transistor with dielectric assisted planarized contacts and method for fabricating A method for fabricating an HBT is disclosed, wherein successive emitter, base, collector and sub-collector epitaxial layers are deposited on a substrate, with the substrate being adjacent to the sub-collector layer. The epitaxial layers are etched to provide locati... | 04/08/2008 |
| 7352201 | System and method for testing devices utilizing capacitively coupled signaling An apparatus and method for testing a semiconductor device in an AC test regime. The test apparatus includes a test plate capacitively couple to the signal terminals of the integrated circuit. The test plate is coupled to a test receiver circuit to receive and outpu... | 04/01/2008 |
| 7348250 | Bipolar structure with two base-emitter junctions in the same circuit Bipolar integrated circuits employing SiGe technology incorporate the provision of mask-selectable types of bipolar transistors. A high-performance/high variability type has a thin base in which the diffusion from the emitter intersects the base dopant diffusion wit... | 03/25/2008 |
| 7303968 | Semiconductor device and method having multiple subcollectors formed on a common wafer A semiconductor device and a method of fabricating a semiconductor device having multiple subcollectors which are formed in a common wafer, in order to provide multiple structures having different characteristic and frequency response are provided. The subcollectors... | 12/04/2007 |
| 7276928 | System and method for testing devices utilizing capacitively coupled signaling An apparatus and method for testing a semiconductor device in an AC test regime. The test apparatus includes a test plate capacitively couple to the signal terminals of the integrated circuit. The test plate is coupled to a test receiver circuit to receive and outpu... | 10/02/2007 |
| 7274204 | System and method for testing devices utilizing capacitively coupled signaling An apparatus and method for testing a semiconductor device in an AC test regime. The test apparatus includes a test plate capacitively couple to the signal terminals of the integrated circuit. The test plate is coupled to a test receiver circuit to receive and outpu... | 09/25/2007 |
| 7274205 | System and method for testing devices utilizing capacitively coupled signaling An apparatus and method for testing a semiconductor device in an AC test regime. The test apparatus includes a test plate capacitively couple to the signal terminals of the integrated circuit. The test plate is coupled to a test receiver circuit to receive and outpu... | 09/25/2007 |
| 7262483 | Semiconductor device and method for manufacturing the same By a non-selective epitaxial growth method, an SiGe film is grown on the whole surface of a silicon oxide film so as to cover an inner wall of a base opening. Here, such film forming conditions are selected that, inside the base opening, a bottom portion is formed o... | 08/28/2007 |
| 7244977 | Longitudinal MISFET manufacturing method, longitudinal MISFET, semiconductor storage device manufacturing method, and semiconductor storage device A semiconductor memory device includes a vertical MISFET having a source region, a channel forming region, a drain region, and a gate electrode formed on a sidewall of the channel forming region via a gate insulating film. In manufacturing the semiconductor memory d... | 07/17/2007 |
| 7229874 | Method and apparatus for allowing formation of self-aligned base contacts A method and apparatus for depositing self-aligned base contacts where over-etching the emitter sidewall to undercut the emitter contact is not needed. A semiconductor structure has a T-shaped emitter contact that comprises a T-top and T-foot. The T-top acts as a ma... | 06/12/2007 |
| 7214593 | Passivation for improved bipolar yield A SiGe heterojunction bipolar transistor including at least an emitter formed on a SiGe base region wherein the sidewalls of the emitter are protected by a conformal passivation layer. The conformal passivation layer is formed on the exposed sidewalls of said emitte... | 05/08/2007 |
| 7214627 | Graded junction termination extensions for electronic devices A graded junction termination extension in a silicon carbide (SiC) semiconductor device and method of its fabrication using ion implementation techniques is provided for high power devices. The properties of silicon carbide (SiC) make this wide band gap semiconducto... | 05/08/2007 |
| 7214616 | Homojunction semiconductor devices with low barrier tunnel oxide contacts A homojunction bipolar transistor with performance characteristics similar to more costly heterojunction or retrograde base transistors. The high emitter resistivity found in prior homojunction devices is circumvented using a low work function material layer in form... | 05/08/2007 |
| 7198998 | Method of manufacturing bipolar-complementary metal oxide semiconductor A method of manufacturing a bipolar-complementary metal oxide semiconductor (BiCMOS) is provided. A gate in a CMOS area and a conductive layer pattern defining an opening, which opens an active region in a bipolar transistor area, are simultaneously formed by patter... | 04/03/2007 |
| 7190047 | Transistors and methods for making the same Apparatus comprising: a first compound semiconductor composition layer doped to have a first charge carrier polarity; a second compound semiconductor composition layer doped to have a second charge carrier polarity and located on the first layer; a third compound se... | 03/13/2007 |
| 7186630 | Deposition of amorphous silicon-containing films Chemical vapor deposition methods are used to deposit amorphous silicon-containing films over various substrates. Such methods are useful in semiconductor manufacturing to provide a variety of advantages, including uniform deposition over heterogeneous surfaces, hig... | 03/06/2007 |
| 7186582 | Process for deposition of semiconductor films Chemical vapor deposition processes utilize higher order silanes and germanium precursors as chemical precursors. The processes have high deposition rates yet produce more uniform films, both compositionally and in thickness, than films prepared using conventional c... | 03/06/2007 |
| 7183627 | Independent control of polycrystalline silicon-germanium in an HBT and related structure In one embodiment a precursor gas for growing a polycrystalline silicon-germanium region and a single crystal silicon-germanium region is supplied. The precursor gas can be, for example, GeH4. The polycrystalline silicon-germanium region can be, for examp... | 02/27/2007 |
| 7183790 | System and method for testing devices utilizing capacitively coupled signaling An apparatus and method for testing a semiconductor device in an AC test regime. The test apparatus includes a test plate capacitively couple to the signal terminals of the integrated circuit. The test plate is coupled to a test receiver circuit to receive and outpu... | 02/27/2007 |
| 7183150 | Resist protect oxide structure of sub-micron salicide process In accordance with the objectives of the invention a new method is provided for the creation of a layer of a Resistance Protective Oxide (RPO) layer. A layer of ONO is deposited that is to function as the layer of RPO. The deposited layer of ONO is patterned and wet... | 02/27/2007 |
| 7180159 | Bipolar transistor having base over buried insulating and polycrystalline regions A bipolar transistor in a monocrystalline semiconductor substrate (101), which has a first conductivity type and includes a surface layer (102) of the opposite conductivity type. The transistor comprises an emitter contact (110) on the surface l... | 02/20/2007 |
| 7173274 | Incorporation of carbon in silicon/silicon germanium epitaxial layer to enhance yield for Si-Ge bipolar technology A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe bas... | 02/06/2007 |
| 7166517 | Semiconductor device and method of manufacture thereof The present invention provides a method of manufacturing a semiconductor device which includes an amorphous semiconductor film forming treatment of supplying a starting material gas containing germanium to a semiconductor substrate, thereby forming an amorphous semi... | 01/23/2007 |
| 7151035 | Semiconductor device and manufacturing method thereof A sidewall-insulation film 9 is provided on a side surface of a first opening portion 8a formed in a base extraction electrode 5B of a hetero-junction bipolar transistor, and a portion of the sidewall-insulation film 9 extends so a... | 12/19/2006 |
| 7132701 | Contact method for thin silicon carbide epitaxial layer and semiconductor devices formed by those methods Provided is a process for forming a contact for a compound semiconductor device without electrically shorting the device. In one embodiment, a highly doped compound semiconductor material is electrically connected to a compound semiconductor material of the same con... | 11/07/2006 |
| 7118995 | Yield improvement in silicon-germanium epitaxial growth A method for determining a SiGe deposition condition so as to improve yield of a semiconductor structure. Fabrication of the semiconductor structure starts with a single-crystal silicon (Si) layer. Then, first and second shallow trench isolation (STI) regions are fo... | 10/10/2006 |
| 7118981 | Method of fabricating an integrated silicon-germanium heterobipolar transistor and an integrated silicon-germanium heterobipolar transistor In a method of fabricating an integrated silicon-germanium heterobipolar transistor a silicon dioxide layer arranged between a silicon-germanium base layer and a silicon emitter layer is formed by means of Rapid Thermal Processing (RTP) to ensure enhanced component ... | 10/10/2006 |
| 7112980 | System and method for testing devices utilizing capacitively coupled signaling An apparatus and method for testing a semiconductor device in an AC test regime. The test apparatus includes a test plate capacitively couple to the signal terminals of the integrated circuit. The test plate is coupled to a test receiver circuit to receive and outpu... | 09/26/2006 |
| 7098114 | Method for forming cmos device with self-aligned contacts and region formed using salicide process A method for forming CMOS devices on a semiconductor substrate is disclosed in which gate structures are formed within both the core region and the non-core region of the semiconductor substrate. The gate structures include a gate dielectric layer and a gate film st... | 08/29/2006 |
| 7091099 | Bipolar transistor and method for fabricating the same A bipolar transistor includes a Si single crystalline layer serving as a collector, a single crystalline Si/SiGeC layer and a polycrystalline Si/SiGeC layer which are formed on the Si single crystalline layer, an oxide film having an emitter opening portion, an emit... | 08/15/2006 |
| 7087940 | Structure and method of forming bipolar transistor having a self-aligned raised extrinsic base using self-aligned etch stop layer A bipolar transistor structure and method of making the bipolar transistor are provided. The bipolar transistor includes a collector region, an intrinsic base layer overlying the collector region, and an emitter overlying the intrinsic base layer. An opened etch sto... | 08/08/2006 |
| 7075330 | System and method for balancing capacitively coupled signal lines A signal balancing circuit for capacitively coupled signaling between transmitting and receiving devices over a plurality of capacitively coupled signal lines on which data signals are transmitted from the transmitting device to the receiving device. The signal bala... | 07/11/2006 |
| 7074685 | Method of fabrication SiGe heterojunction bipolar transistor A method of fabricating a semiconductor device includes a SiGe(C) heterojunction bipolar transistor using a non-selective epitaxial growth where an insulating layer is formed on a substrate and a layer structure including a conductive layer is provided on the insula... | 07/11/2006 |
| 7067898 | Semiconductor device having a self-aligned base contact and narrow emitter A semiconductor structure having a self-aligned base contact and an emitter, where the base contact is electrically isolated from the emitter by a dielectric layer. The separation between the base contact and the emitter is determined by the thickness of the dielect... | 06/27/2006 |
| 7064360 | Bipolar transistor and method for fabricating it A method is provided to fabricate a bipolar transistor with a low base connection resistance, low defect density and improved scalability. Scalability is to be understood in this case as both the lateral scaling of the emitter window and the vertical scaling of the ... | 06/20/2006 |
| 7049201 | Method and apparatus for a heterojunction bipolar transistor using self-aligned epitaxy A heterojunction bipolar transistor (HBT), and manufacturing method therefor, comprising a semiconductor substrate having a collector region, a number of insulating layers over the semiconductor substrate, at least one of the number of insulating layers having a bas... | 05/23/2006 |
