Bizarre Patents
A gun that fires a missile, powered by gas "discharged by the operator of the toy."
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8101491 | Heterojunction bipolar transistor According to an example embodiment, a heterostructure bipolar transistor, HBT, includes shallow trench isolation, STI, structures around a buried collector drift region in contact with a buried collector. A gate stack including a gate oxide and a gate is deposited a... | 01/24/2012 |
| 7923340 | Method to reduce collector resistance of a bipolar transistor and integration into a standard CMOS flow The invention, in one aspect, provides a method for fabricating a semiconductor device. In one aspect, the method provides for a dual implantation of a tub of a bipolar transistor. The tub in bipolar region is implanted by implanting the tub through separate implant... | 04/12/2011 |
| 7838374 | Method of manufacturing a bipolar transistor The invention relates to a method of manufacturing a bipolar transistor on a semiconductor substrate (11) which is provided with a first, a second and a third layer (1,2,3) of a first, second and third semiconductor material respectively, all of a firs... | 11/23/2010 |
| 7462547 | Method of fabricating a bipolar transistor having reduced collector-base capacitance A method is provided for fabricating a bipolar transistor that includes growing an epitaxial layer onto an underlaying region having a low dopant concentration and a trench isolation region defining the edges of an active region layer, implanting a portion of the ep... | 12/09/2008 |
| 7422951 | Method of fabricating self-aligned bipolar transistor The present invention provides a method of fabricating a self-aligned bipolar transistor, by which the fabricating method can be simplified by forming P+ and N+ junctions by self-alignment and by which device reliability can be enhanced. The present invention includ... | 09/09/2008 |
| 7364832 | Wet developable hard mask in conjunction with thin photoresist for micro photolithography A novel process for using a hard mask or protective layer in conjunction with an extremely thin photoresist is provided. In this process, a thin film of the protective layer is coated on the surface of a substrate that is to be selectively modified by reactive ion e... | 04/29/2008 |
| 7354840 | Method for opto-electronic integration on a SOI substrate According to an exemplary embodiment, a method includes providing a silicon-on-insulator substrate including a buried oxide layer situated over a bulk silicon substrate and a silicon layer situated over the buried oxide layer. A trench is formed in the silicon layer... | 04/08/2008 |
| 7354812 | Multiple-depth STI trenches in integrated circuit fabrication Multiple trench depths within an integrated circuit device are formed by first forming trenches in a substrate to a first depth, but of varying widths. Formation of a dielectric layer can cause some of the trenches to fill or close off while leaving other, wider tre... | 04/08/2008 |
| 7329584 | Method for manufacturing bipolar transistor A method for manufacturing a bipolar transistor includes: forming a device isolation layer on a semiconductor substrate having first and second well regions of a first conductivity therein; implanting ions of a second conductivity in the first well to form a third w... | 02/12/2008 |
| 7303968 | Semiconductor device and method having multiple subcollectors formed on a common wafer A semiconductor device and a method of fabricating a semiconductor device having multiple subcollectors which are formed in a common wafer, in order to provide multiple structures having different characteristic and frequency response are provided. The subcollectors... | 12/04/2007 |
| 7271011 | Methods of implementing magnetic tunnel junction current sensors Techniques are provided for sensing a first current produced by an active circuit component. According to these techniques, a current sensor is disposed over the active circuit component. The current sensor includes a Magnetic Tunnel Junction (“MTJ”) core dispos... | 09/18/2007 |
| 7268376 | Bipolar transistor for increasing signal transfer efficiency and method of manufacturing the same A bipolar transistor having a base semiconductor layer structure to minimize base parasitic resistance and a method of manufacturing the bipolar transistor are provided. In the provided bipolar transistor, a collector region of a second conductivity type, which is d... | 09/11/2007 |
| 7262483 | Semiconductor device and method for manufacturing the same By a non-selective epitaxial growth method, an SiGe film is grown on the whole surface of a silicon oxide film so as to cover an inner wall of a base opening. Here, such film forming conditions are selected that, inside the base opening, a bottom portion is formed o... | 08/28/2007 |
| 7253042 | Method of fabricating a high-voltage transistor with an extended drain structure A method for fabricating a high-voltage transistor with an extended drain region includes forming in a semiconductor substrate of a first conductivity type, first and second trenches that define a mesa having respective first and second sidewalls; then partially fil... | 08/07/2007 |
| 7214593 | Passivation for improved bipolar yield A SiGe heterojunction bipolar transistor including at least an emitter formed on a SiGe base region wherein the sidewalls of the emitter are protected by a conformal passivation layer. The conformal passivation layer is formed on the exposed sidewalls of said emitte... | 05/08/2007 |
| 7189619 | Process for manufacturing vertically insulated structural components on SOI material of various thickness Vertically insulated active semiconductor regions having different thicknesses in an SOI wafer, which has an insulating layer, is produced. On the wafer, first active semiconductor regions having a first thickness are arranged in a layer of active semiconductor mate... | 03/13/2007 |
| 7190046 | Bipolar transistor having reduced collector-base capacitance Structure and method are provided for forming a bipolar transistor. As disclosed, an intrinsic base layer is provided overlying a collector layer. A low-capacitance region is disposed laterally adjacent the collector layer. The low-capacitance region includes at lea... | 03/13/2007 |
| 7186582 | Process for deposition of semiconductor films Chemical vapor deposition processes utilize higher order silanes and germanium precursors as chemical precursors. The processes have high deposition rates yet produce more uniform films, both compositionally and in thickness, than films prepared using conventional c... | 03/06/2007 |
| 7183627 | Independent control of polycrystalline silicon-germanium in an HBT and related structure In one embodiment a precursor gas for growing a polycrystalline silicon-germanium region and a single crystal silicon-germanium region is supplied. The precursor gas can be, for example, GeH4. The polycrystalline silicon-germanium region can be, for examp... | 02/27/2007 |
| 7176098 | Semiconductor element and method for fabricating the same A heterojunction bipolar transistor comprises a collector layer, a base layer formed on the collector layer and an emitter layer formed on the base layer. The emitter layer includes a first semiconductor layer covering the entire top surface of the base layer and a ... | 02/13/2007 |
| 7173274 | Incorporation of carbon in silicon/silicon germanium epitaxial layer to enhance yield for Si-Ge bipolar technology A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe bas... | 02/06/2007 |
| 7172914 | Method of making uniform oxide layer A method of forming a semiconductor structure includes forming an isolation region in a semiconductor substrate. A first oxide layer is on the substrate, a first sacrificial layer is on the first oxide layer, and a first nitride layer is on the first sacrificial lay... | 02/06/2007 |
| 7157344 | Vapor-phase growth method, semiconductor manufacturing method and semiconductor device manufacturing method In a vapor-phase growth method in which a silicon-germanium mixed crystal layer is deposited on a semiconductor substrate, the vapor-phase growth method comprises a first step of introducing silicon raw material gas into a reaction furnace in such a manner that a si... | 01/02/2007 |
| 7151035 | Semiconductor device and manufacturing method thereof A sidewall-insulation film 9 is provided on a side surface of a first opening portion 8a formed in a base extraction electrode 5B of a hetero-junction bipolar transistor, and a portion of the sidewall-insulation film 9 extends so a... | 12/19/2006 |
| 7148115 | Semiconductor device and method for forming the same The present invention is related to semiconductor device and method for manufacturing the same. In accordance with the semiconductor device and method for manufacturing the same, at least one opening extending between LDD regions and exposing a buried insulating lay... | 12/12/2006 |
| 7141478 | Multi-stage EPI process for forming semiconductor devices, and resulting device The present invention is generally directed to a multi-stage epi process for forming semiconductor devices, and the resulting device. In one illustrative embodiment, the method comprises forming a first layer of epitaxial silicon above a surface of a semiconducting ... | 11/28/2006 |
| 7141479 | Bipolar transistor and method for producing the same A method for producing a bipolar transistor is described, which comprises providing a layer sequence, which comprises a substrate, a first oxide layer and a SOI layer, generating a collector region in the substrate, generating a second oxide layer on the layer seque... | 11/28/2006 |
| 7132338 | Methods to fabricate MOSFET devices using selective deposition process In one embodiment, a method for fabricating a silicon-based device on a substrate surface is provided which includes depositing a first silicon-containing layer by exposing the substrate surface to a first process gas comprising Cl2SiH2, a germ... | 11/07/2006 |
| 7132701 | Contact method for thin silicon carbide epitaxial layer and semiconductor devices formed by those methods Provided is a process for forming a contact for a compound semiconductor device without electrically shorting the device. In one embodiment, a highly doped compound semiconductor material is electrically connected to a compound semiconductor material of the same con... | 11/07/2006 |
| 7118981 | Method of fabricating an integrated silicon-germanium heterobipolar transistor and an integrated silicon-germanium heterobipolar transistor In a method of fabricating an integrated silicon-germanium heterobipolar transistor a silicon dioxide layer arranged between a silicon-germanium base layer and a silicon emitter layer is formed by means of Rapid Thermal Processing (RTP) to ensure enhanced component ... | 10/10/2006 |
| 7119023 | Process integration of SOI FETs with active layer spacer A method of manufacturing a microelectronics device including providing a substrate having an active layer, a dielectric layer and a structural layer, wherein the active layer is formed over the dielectric layer and the dielectric layer is formed over the structural... | 10/10/2006 |
| 7088168 | Direct conversion receiver using vertical bipolar junction transistor available in deep n-well CMOS technology This invention is about the direct conversion receiver. It is excellent the receiving sensitivity that DC off-set, matching characteristics of the relationship of I/Q circuits and noise characteristics are improved. In order to achieve this purpose, the direct conve... | 08/08/2006 |
| 7075126 | Transistor structure with minimized parasitics and method of fabricating the same A transistor having minimized parasitics is provided including an emitter having a recessed extrinsic emitter portion atop an intrinsic emitter portion; a base including an intrinsic base portion in electrical contact with the intrinsic emitter portion and an extrin... | 07/11/2006 |
| 7074685 | Method of fabrication SiGe heterojunction bipolar transistor A method of fabricating a semiconductor device includes a SiGe(C) heterojunction bipolar transistor using a non-selective epitaxial growth where an insulating layer is formed on a substrate and a layer structure including a conductive layer is provided on the insula... | 07/11/2006 |
| 7064416 | Semiconductor device and method having multiple subcollectors formed on a common wafer A semiconductor device and a method of fabricating a semiconductor device having multiple subcollectors which are formed in a common wafer, in order to provide multiple structures having different characteristic and frequency response are provided. The subcollectors... | 06/20/2006 |
| 7038250 | Semiconductor device suited for a high frequency amplifier According to the present invention, there is a provided a semiconductor device having, a collector contact layer made of an n-type GaAs layer; a first collector layer formed on the collector contact layer and made of an n-type GaAs layer; a second collector layer fo... | 05/02/2006 |
| 7037798 | Bipolar transistor structure with self-aligned raised extrinsic base and methods The invention includes methods of fabricating a bipolar transistor that adds a silicon germanium (SiGe) layer or a third insulator layer of, e.g., high pressure oxide (HIPOX), atop an emitter cap adjacent the intrinsic base prior to forming a link-up layer. This add... | 05/02/2006 |
| 7033896 | Field effect transistor with a high breakdown voltage and method of manufacturing the same An electric field effect transistor of high breakdown voltage and a method of manufacturing the same are disclosed. A recessed portion is formed at the channel region and is filled by a protective oxide layer. Lightly doped source/drain regions are formed under the ... | 04/25/2006 |
| 7012009 | Method for improving the electrical continuity for a silicon-germanium film across a silicon/oxide/polysilicon surface using a novel two-temperature process A method for making an improved silicon-germanium layer on a substrate for the base of a heterojunction bipolar transistor is achieved using a two-temperature process. The method involves growing a seed layer at a higher temperature to reduce the grain size with sho... | 03/14/2006 |
| 7008852 | Discontinuous dielectric interface for bipolar transistors A process for forming at least one interface region between two regions of semiconductor material. At least one region of dielectric material comprising nitrogen is formed in the vicinity of at least a portion of a boundary between the two regions of semiconductor m... | 03/07/2006 |
