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| Number | Title | Issue Date |
| 7342276 | Method and apparatus utilizing monocrystalline insulator A semiconductor device, including: a semiconductor material; a conductive element; and a substantially monocrystalline insulator disposed between the semiconductor material and the conductive eleme... | 03/11/2008 |
| 7285457 | Heterojunction bipolar transistor and manufacturing method thereof In the method for manufacturing a heterojunction bipolar transistor, a collector contact layer, a collector layer, a base layer, a base protection layer, an emitter layer, an emitter contact layer, and a WSi layer are sequentially formed on a substrate. A resist pat... | 10/23/2007 |
| 7276744 | Semiconductor device and method of manufacturing the same This invention is intended to provide an HBT capable of achieving, if the HBT is a collector-up HBT, the constriction of the emitter layer disposed directly under an external base layer, and reduction in base-emitter junction capacity, or if the HBT is an emitter-up... | 10/02/2007 |
| 7262484 | Structure and method for performance improvement in vertical bipolar transistors A method of forming a semiconductor device having two different strains therein is provided. The method includes forming a strain in a first region with a first straining film, and forming a second strain in a second region with a second straining film. Either of th... | 08/28/2007 |
| 7256433 | Bipolar transistor and a method of manufacturing the same A bipolar transistor having enhanced characteristics is fabricated by etching a base mesa, which is formed below an emitter mesa (upper emitter layer) and a base electrode, so as to have jut regions on the edges of its generally rectangular region. A mask film, e.g.... | 08/14/2007 |
| 7250340 | Method of fabricating programmable structure including discontinuous storage elements and spacer control gates in a trench A method of fabricating a semiconductor storage cell that includes first and second source/drain regions underlying first and second trenches defined in a semiconductor substrate. Sidewalls of the trenches are lined with a charge storage stack that includes a layer ... | 07/31/2007 |
| 7244974 | wideband gap power semiconductor device having a low on-resistance and having a high avalanche capability used for power control A power semiconductor device includes a first semiconductor layer, a second semiconductor layer of a first conductivity type, first and second main electrodes, a control electrode and a third semi-conductor layer. The second semiconductor layer is formed on the firs... | 07/17/2007 |
| 7230285 | Semiconductor device and hetero-junction bipolar transistor In an npn-type HBT, each of an emitter layer and a collector layer is formed of AlGaN and a base layer is formed of GaN. The emitter layer is in contact with a nitrogen polarity surface of the base layer and the collector layer is in contact with a gallium polarity ... | 06/12/2007 |
| 7176098 | Semiconductor element and method for fabricating the same A heterojunction bipolar transistor comprises a collector layer, a base layer formed on the collector layer and an emitter layer formed on the base layer. The emitter layer includes a first semiconductor layer covering the entire top surface of the base layer and a ... | 02/13/2007 |
| 7132320 | Method for manufacturing semiconductor device The present invention achieves the enhancement of a manufacturing yield factor and the reduction of manufacturing cost in a manufacturing method of a semiconductor device having a hetero junction bipolar transistor (HBT), a Schottky diode and a resistance element. T... | 11/07/2006 |
| 7118965 | Methods of fabricating nonvolatile memory device A fabricating method of a nonvolatile memory device is disclosed. A disclosed method comprises: implanting ions into an active region of a semiconductor substrate to form a well of a low voltage transistor and adjust its threshold voltage; implanting ions into an ac... | 10/10/2006 |
| 7037786 | Method of forming a low voltage gate oxide layer and tunnel oxide layer in an EEPROM cell A method of fabricating a non-volatile memory embedded logic circuit having a low voltage logic gate oxide layer and tunnel oxide layer is described. Both the low voltage logic gate oxide and the tunnel oxide layers are formed in a single step, thereby reducing the ... | 05/02/2006 |
| 7015539 | Nonvolatile semiconductor memory cell and method of manufacturing the same A stacked-gate structure includes a tunnel insulation film, a floating gate electrode, an inter-electrode insulation film and a control gate electrode, which are stacked on a semiconductor substrate. The inter-electrode insulation film has a three-layer structure th... | 03/21/2006 |
| 7015588 | Semiconductor device According to a semiconductor device of the present invention, a layer of an electric insulator is provided on a semiconductor substrate. A connection pad having a part exposed to a layer surface is provided in the layer. A transistor structure opposed to the connect... | 03/21/2006 |
| 6927413 | Semiconductor device including band-engineered superlattice A semiconductor device includes a superlattice that, in turn, includes a plurality of stacked groups of layers. The device may also include regions for causing transport of charge carriers through the superlattice in a parallel direction relative to the stacked grou... | 08/09/2005 |
| 6913981 | Method of fabricating a bipolar transistor using selective epitaxially grown SiGe base layer Embodiments of a bipolar transistor are disclosed, along with methods for making the transistor. An exemplary transistor includes a collector region in a semiconductor substrate, a base layer overlying the collector region and bound by a field oxide layer, a dielect... | 07/05/2005 |
| 6911370 | Flash memory device having poly spacers A non-volatile memory device includes a substrate having a first active region and a second active region. A first floating gate is provided over the first active region and having an edge, the first floating gate being made of a conductive material. A first spacer ... | 06/28/2005 |
| 6903386 | Transistor with means for providing a non-silicon-based emitter A transistor includes a means for providing a non-silicon-based emitter with a flexible structure to relieve lattice mis-match between the emitter and the base. ... | 06/07/2005 |
| 6875649 | Methods for manufacturing integrated circuit devices including an isolation region defining an active region area Integrated circuit devices including an isolation region are provided. The devices include an integrated circuit substrate and a trench in the integrated circuit substrate that defines an active region of the integrated circuit device. A silicon layer is provided on... | 04/05/2005 |
| 6858509 | Bipolar transistor with upper heterojunction collector and method for making same A collector-up heterojunction bipolar transistor including, stacked on a substrate, an emitter layer, a base layer, and a collector layer. In this transistor the surface area of the base-emitter junction is of smaller dimensions than the surface area of the base-col... | 02/22/2005 |
| 6833308 | Structure and method for dual gate oxide thicknesses Structures and methods involving at least a pair of gate oxides having different thicknesses, one suitable for use in a logic device and one suitable for use in a memory device, have been shown. The method provided by the present invention affords a technique for ul... | 12/21/2004 |
| 6815272 | Bottom gate-type thin-film transistor and method for manufacturing the same In a bottom gate-type thin-film transistor manufacturing method, after ion doping, an ion stopper is removed. The ion stopper does not remain in the interlayer insulating film lying immediately above the gate electrode. The thin-film transistor has such a structure ... | 11/09/2004 |
| 6777302 | Nitride pedestal for raised extrinsic base HBT process A method of fabricating a high-performance, raised extrinsic base HBT having a narrow emitter width is provided. In accordance with the method, a patterned nitride pedestal region and inner spacers are employed to reduce the width of an emitter opening. The reduced ... | 08/17/2004 |
| 6777301 | Method of producing hetero-junction bipolar transistor A method of producing a hetero-junction bipolar transistor includes: laminating semiconductor layers that are to be a subcollector layer, a collector layer, a base layer, an emitter layer and an emitter cap layer successively on one surface of a semi-insulating subs... | 08/17/2004 |
| 6683364 | Integrated circuit devices including an isolation region defining an active region area and methods for manufacturing the same Integrated circuit devices including an isolation region are provided. The devices include an integrated circuit substrate and a trench in the integrated circuit substrate that defines an active region of the integrated circuit device. A silicon layer is ... | 01/27/2004 |
| 6649472 | Method of manufacturing a flash memory cell with high programming efficiency by coupling from floating gate to sidewall A new method to form flash memory devices in the manufacture of an integrated circuit device is achieved. The method comprises providing a substrate. A first film is formed comprising a first oxide layer overlying the substrate and a floating gate layer o... | 11/18/2003 |
| 6624017 | Manufacturing process of a germanium implanted HBT bipolar transistor A process fabricates a vertical structure high carrier mobility transistor on a substrate of crystalline silicon doped with impurities of the N type, the transistor having a collector region located at a lower portion of the substrate. The process include... | 09/23/2003 |
| 6605519 | Method for thin film lift-off processes using lateral extended etching masks and device A method for forming an etching mask structure on a substrate includes etching the substrate, laterally expanding the etching mask structure, and depositing a self-aligned metal layer that is aligned to the originally masked area. The etching can be isotr... | 08/12/2003 |
| 6579752 | Phosphorus dopant control in low-temperature Si and SiGe epitaxy A method of manufacturing a semiconductor device comprising the step of epitaxially growing of an n-type doped layer of a semiconductor material using an n-type dopant gas, the growth process being performed at a pressure higher than 2.66×104 ... | 06/17/2003 |
| 6570215 | Nonvolatile memories with floating gate spacers, and methods of fabrication In a nonvolatile memory, a floating gate includes a portion of a conductive layer (150), and also includes conductive spacers (610). The spacers increase the capacitive coupling between the floating gate and the control gate (170).... | 05/27/2003 |
| 6506670 | Self aligned gate A method for making a gate in an integrated circuit. A gate layer is formed on a substrate, and a blocking layer is formed on the gate layer. The blocking layer is masked with a photoresist layer, and the photoresist layer is developed to define an expose... | 01/14/2003 |
| 6500721 | Bipolar thin-film transistors and method for forming A bipolar junction transistor includes a substrate, a first layer, a second layer, and a third layer. The first layer comprises non-single-crystalline semiconductor material having a first conductivity type deposited on the substrate. The second layer com... | 12/31/2002 |
| 6461927 | Semiconductor device and method of producing the same In the case of a semiconductor device where a base electrode 11 in a collector top heterojunction bipolar transistor is disposed so as to contact with the side face of a base layer 5 in which no ion is implanted and the surface of a high resistance extrin... | 10/08/2002 |
| 6436765 | Method of fabricating a trenched flash memory cell A method of fabricating a trenched flash memory cell is provided. A plurality of shallow trench isolation structures are formed to enclose at least an active area in a silicon substrate. A doped region is formed in the silicon substrate, followed by the d... | 08/20/2002 |
| 6426266 | Manufacturing method for an inverted-structure bipolar transistor with improved high-frequency characteristics In an element intrinsic region 12 of a bipolar transistor, an emitter is formed by two emitter layers 31,32 so as to reduce the potential barrier presented to minority carriers, this resulting in a smooth flow of minority carriers that are injected into t... | 07/30/2002 |
| 6329259 | Collector-up RF power transistor A method for manufacturing a low voltage high frequency silicon power transistor applying epitaxial mesa structure using a minimized number of masks has a highly doped silicon n++ substrate forming the emitter. Also a low voltage high frequency... | 12/11/2001 |
| 6281089 | Method for fabricating an embedded flash memory cell A method for embedded flash cell fabrication beyond 0.35 .XI.m generation. First, a relatively thick field oxide layer is formed on the P-type substrate to separate the flash cell areas and logic cell area. The flash cell areas are divided into tunnel oxi... | 08/28/2001 |
| 6150224 | Method of manufacturing a semiconductor device with a bipolar transistor The invention relates to the manufacture of a so-called differential bipolar transistor comprising a base (1A), an emitter (2) and a collector (3), the base (1A) being formed by applying a doped semiconducting layer (1) which locally borders on a monocrys... | 11/21/2000 |
| 6090675 | Formation of dielectric layer employing high ozone:tetraethyl-ortho-silicate ratios during chemical vapor deposition A method for forming upon a microelectronics layer upon a substrate employed within a microelectronics fabrication a silicon oxide dielectric layer with enhanced density and reduced mobile species, ionic concentration and ionic mobility. There is provided... | 07/18/2000 |
| 5943577 | Method of making heterojunction bipolar structure having air and implanted isolations In a method manufacturing a semiconductor device, a semiconductor layer having a device forming region is formed on substrate. Next, a region except for the device forming region is changed into an insulator. In this case, a conducting path is left across... | 08/24/1999 |
