Did You Know...
...that after Parker Brothers executives turned down the game of Monopoly because it had "52 fundamental errors" (including taking too long to play), a copy of the game wound up in the home of the company president who stayed up until 1 a.m. to finish playing it? He was so impressed by the game that the next day he wrote to inventor Charles Darrow and offered to buy it!
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| Number | Title | Issue Date |
| 8133791 | Method of manufacturing a bipolar transistor and bipolar transistor obtained therewith The invention relates to a method according to the part of the surface of the semiconductor body adjoining the opening and which is to be kept free is provided with a cover layer after which the high-crystalline layer is formed by means of a deposition process. The ... | 03/13/2012 |
| 8039352 | Polarization-induced barriers for N-face nitride-based electronics A method for fabricating a potential barrier for a nitrogen-face (N-face) nitride-based electronic device, comprising using a thickness and polarization induced electric field of a III-nitride interlayer, positioned between a first III-nitride layer and a second III... | 10/18/2011 |
| 8026146 | Method of manufacturing a bipolar transistor The invention provides for an alternative and less complex method of manufacturing a bipolar transistor comprising a field plate (17) in a trench (7) adjacent to a collector region (21), which field plate (17) employs a reduced surface fi... | 09/27/2011 |
| 7851319 | Method for preparing a non-self-aligned heterojunction bipolar transistor with a small emitter-to-base spacing The present invention refers to a method for preparing a non-self-aligned heterojunction bipolar transistor comprising: preparing a patterned emitter metal on an emitter epi layer of a HBT epi structure on a substrate; preparing an emitter epitaxy below the emitter ... | 12/14/2010 |
| 7846806 | System and method for providing a self aligned silicon germanium (SiGe) heterojunction bipolar transistor using a mesa emitter-base architecture A system and method are disclosed for providing a self aligned silicon germanium (SiGe) heterojunction bipolar transistor using a mesa emitter-base architecture. The transistor of the present invention comprises a non-selective epitaxial growth (NSEG) collector, an ... | 12/07/2010 |
| 7803685 | Silicided base structure for high frequency transistors High frequency performance of (e.g., silicon) bipolar devices (100, 100″) is improved by reducing the extrinsic base resistance Rbx. Emitter (160), base (161) and collector (190) are formed in or on a semiconductor substrate (110... | 09/28/2010 |
| 7781295 | System and method for providing a single deposition emitter/base in a bipolar junction transistor A system and method is disclosed for manufacturing a bipolar junction transistor that comprises an emitter/base layer that is formed by a single deposition process. In one advantageous embodiment of the invention the emitter/base layer comprises an emitter layer tha... | 08/24/2010 |
| 7655528 | Manufacturing method of semiconductor device SiH3CH3 having the concentration of 1 to 10% is diluted with H2 and a portion of the diluted SiH3CH3, GeH4 and SiH4 (or DCS) are respectively supplied to a chamber of an epitaxial device at... | 02/02/2010 |
| 7655529 | InP based heterojunction bipolar transistors with emitter-up and emitter-down profiles on a common wafer A wafer comprising at least one emitter-up Heterojunction Bipolar Transistor (HBT) and at least one emitter-down HBT on a common InP based semiconductor wafer. Isolation and N-type implants into the device layers differentiate an emitter-down HBT from an emitter-up ... | 02/02/2010 |
| 7651919 | Bandgap and recombination engineered emitter layers for SiGe HBT performance optimization A method for fabricating a heterojunction bipolar transistor (HBT) is provided. The method includes providing a substrate including a collector region; forming a compound base region over the collector region; and forming an emitter region over the compound base reg... | 01/26/2010 |
| 7598148 | Non-self-aligned heterojunction bipolar transistor and a method for preparing a non-self-aligned heterojunction bipolar transistor The present invention refers to a method for preparing a non-self-aligned heterojunction bipolar transistor comprising: preparing a patterned emitter metal on an emitter epi layer of a HBT epi structure on a substrate; preparing an emitter epitaxy below the emitter ... | 10/06/2009 |
| 7582536 | Electronic device with reduced interface charge between epitaxially grown layers and a method for making the same An electronic device contains a substrate, a sub-collector supported by the substrate, an un-doped layer having a selectively implanted buried sub-collector and supported by the sub-collector, an As-based nucleation layer partially supported by the un-doped layer, a... | 09/01/2009 |
| 7524730 | Method of fabricating bipolar junction transistor A method of fabricating a bipolar junction transistor is provided herein. An isolation structure is formed on a first conductive type substrate. A second conductive type deep well is formed in the first conductive type substrate to serve as a collector. Thereafter, ... | 04/28/2009 |
| 7494888 | Device and method using isotopically enriched silicon The present invention provides a process for manufacturing a semiconductor device that can be incorporated into an integrated circuit. The method includes, forming a first doped layer of isotopically enriched silicon over a foundational substrate, forming a second l... | 02/24/2009 |
| 7432539 | Imaging method utilizing thyristor-based pixel elements An improved imaging array (and corresponding method of operation) includes a plurality of heterojunction thyristor-based pixel elements disposed within resonant cavities formed on a substrate. Each thyristor-based pixel element includes complementary n-type and p-ty... | 10/07/2008 |
| 7414298 | Super self-aligned collector device for mono-and hetero bipolar junction transistors, and method of making same The invention relates to a process of forming a compact bipolar junction transistor (BJT) that includes forming a self-aligned collector tap adjacent the emitter stack and an isolation structure. A base layer is formed from epitaxial silicon that is disposed in the ... | 08/19/2008 |
| 7413963 | Method of edge bevel rinse A method of edge bevel rinse. First, a wafer having a coating material layer disposed thereon is provided. A light beam is optically projected on the wafer to form a reference pattern. The reference pattern defines a central region, and a bevel region surrounding th... | 08/19/2008 |
| 7396731 | Method for preparing a non-self-aligned heterojunction bipolar transistor with a small emitter-to-base spacing The present invention refers to a method for preparing a non-self-aligned heterojunction bipolar transistor comprising: preparing a patterned emitter metal on an emitter epi layer of a HBT epi structure on a substrate; preparing an emitter epitaxy below the emitter ... | 07/08/2008 |
| 7390721 | Methods of base formation in a BiCMOS process Methods for fabricating a heterojunction bipolar transistor having a raised extrinsic base is provided in which the base resistance is reduced by forming a silicide atop the raised extrinsic base that extends to the emitter region in a self-aligned manner. The silic... | 06/24/2008 |
| 7390720 | Local collector implant structure for heterojunction bipolar transistors and method of forming the same A bipolar transistor structure includes an intrinsic base layer formed over a collector layer, an emitter formed over the intrinsic base layer, and an extrinsic base layer formed over the intrinsic layer and adjacent the emitter. A ring shaped collector implant stru... | 06/24/2008 |
| 7371671 | System and method for photolithography in semiconductor manufacturing A method for forming a semiconductor device includes forming a photoresist layer over a substrate and patterning the photoresist layer to form photoresist portions. A second layer is formed over the substrate in areas not covered by the photoresist portions and the ... | 05/13/2008 |
| 7368764 | Heterojunction bipolar transistor and method to make a heterojunction bipolar transistor A heterojunction bipolar transistor and a method of making a heterojunction bipolar transistor. The heterojunction bipolar transistor includes: a regrown emitter region; an intrinsic base region forming a junction with the regrown emitter region; and an extrinsic ba... | 05/06/2008 |
| 7364977 | Heterojunction bipolar transistor and method of fabricating the same Disclosed are a heterojunction bipolar transistor and a method of fabricating the same. A first dielectric layer easily etched is deposited on the overall surface of a substrate before an isolation region is defined. The first dielectric layer and a sub-collector la... | 04/29/2008 |
| 7358545 | Bipolar junction transistor A bipolar junction transistor is provided. A p-type well region surrounds an n-type emitter and connects with the bottom of the emitter to serve as a base. A p-type base pick-up region connects with the base and surrounds the emitter. An n-type deep well, connected ... | 04/15/2008 |
| 7358131 | Methods of forming SRAM constructions The invention includes SRAM constructions comprising at least one transistor device having an active region extending into a crystalline layer comprising Si/Ge. A majority of the active region within the crystalline layer is within a single crystal of the crystallin... | 04/15/2008 |
| 7354815 | Method for fabricating semiconductor devices using strained silicon bearing material A method of manufacturing an integrated circuit on semiconductor substrates. The method includes providing a semiconductor substrate characterized by a first lattice with a first structure and a first spacing. The semiconductor substrate has an overlying film of mat... | 04/08/2008 |
| 7342293 | Bipolar junction transistors (BJTS) with second shallow trench isolation (STI) regions, and methods for forming same The present invention relates to bipolar junction transistors (BJTS). The collector region of each BJT is located in a semiconductor substrate surface and adjacent to a first shallow trench isolation (STI) region. A second STI region is provided, which extends betwe... | 03/11/2008 |
| 7339267 | Semiconductor package and method for forming the same Semiconductor packages (100) that prevent the leaching of gold from back metal layers (118) into the solder (164) and methods for fabricating the same are provided. An exemplary method comprises providing a semiconductor wafer stack (110)... | 03/04/2008 |
| 7329941 | Creating increased mobility in a bipolar device The mobility of charge carriers in a bipolar (BJT) device is increased by creating compressive strain in the device to increase mobility of electrons in the device, and creating tensile strain in the device to increase mobility of holes in the device. The compressiv... | 02/12/2008 |
| 7323390 | Semiconductor device and method for production thereof The semiconductor device according to the invention includes a substrate, a field insulating region which delimits an active region of the semiconductor substrate, a collector, at least one collector contact region associated with the collector, and a base with an a... | 01/29/2008 |
| 7323728 | Semiconductor device Disclosed is a semiconductor device including an n+-type semiconductor layer formed on a substrate, a first n-type semiconductor layer formed on the n+-type semiconductor layer, a p-type semiconductor layer formed on the first n-type semiconduc... | 01/29/2008 |
| 7323725 | Semiconductor device The present invention relates to a semiconductor device having a multi-layered structure comprising an emitter layer, a base layer, and a collector layer, each composed of a group III-V n-type compound semiconductor in this order; a quantum dot barrier layer dispose... | 01/29/2008 |
| 7320896 | Infrared radiation detector Electronic devices are disclosed that may be used for infrared radiation detection. An example electronic device includes a substrate, a transistor included in the substrate and a silicon-germanium (Si—Ge) structural layer coupled with the transistor. The structur... | 01/22/2008 |
| 7317215 | SiGe heterojunction bipolar transistor (HBT) A heterojunction bipolar transistor is formed in a semiconductor substrate of a first conductivity type including a collector region. A base region is formed on the substrate and an emitter region is formed over the base region. At least one of the collector, base a... | 01/08/2008 |
| 7312128 | Selective epitaxy process with alternating gas supply In one example, a method of epitaxially forming a silicon-containing material on a substrate surface is presented which includes positioning a substrate into a process chamber. The substrate has a monocrystalline surface and at least a second surface, such as an amo... | 12/25/2007 |
| 7303968 | Semiconductor device and method having multiple subcollectors formed on a common wafer A semiconductor device and a method of fabricating a semiconductor device having multiple subcollectors which are formed in a common wafer, in order to provide multiple structures having different characteristic and frequency response are provided. The subcollectors... | 12/04/2007 |
| 7300849 | Bandgap engineered mono-crystalline silicon cap layers for SiGe HBT performance enhancement A method for fabricating a heterojunction bipolar transistor (HBT) is provided. The method includes providing a substrate including a collector region; forming a compound base region over the collector region; forming a cap layer overlying the compound base region i... | 11/27/2007 |
| 7297589 | Transistor device and method A method for making a heterojunction bipolar transistor includes the following steps: forming a heterojunction bipolar transistor by depositing, on a substrate, subcollector, collector, base, and emitter regions of semiconductor material; the step of depositing the ... | 11/20/2007 |
| 7297992 | Method and structure for integration of phosphorous emitter in an NPN device in a BiCMOS process According to one exemplary embodiment, a heterojunction bipolar transistor includes a base situated on a substrate. The heterojunction bipolar transistor can be an NPN silicon-germanium heterojunction bipolar transistor, for example. The heterojunction bipolar trans... | 11/20/2007 |
| 7297993 | Bipolar transistor and fabrication method of the same A bipolar transistor having a base electrode of an air bridge structure is simplified in structure and enhanced in the degree of freedom of a contact position of a base wiring line with the base electrode. The bipolar transistor has a semiconductor mesa portion havi... | 11/20/2007 |
