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| Number | Title | Issue Date |
| 6455390 | Method of manufacturing hetero-junction bipolar transistor A method of manufacturing a hetero-junction bipolar transistor including a carbon-doped base layer includes the steps of (a) growing a base layer on an underlying layer through chemical vapor deposition, (b) forming at least one semiconductor layer over t... | 09/24/2002 |
| 6440810 | Method in the fabrication of a silicon bipolar transistor In the fabrication of a silicon bipolar transistor, a method for forming base regions and for opening an emitter window is provided. A silicon substrate is provided with suitable device isolation. A first base region is formed in or on top of the substrat... | 08/27/2002 |
| 6440809 | Method of preventing fluorine ions from residing in a gate to result in boron ion penetration into a gate oxide The present invention provides a method of preventing fluorine ions from residing in a gate to result in boron ion penetration into a gate oxide on a semiconductor wafer. A substrate, an oxide layer, a conductive layer, an anti-reflection coating (ARC), a... | 08/27/2002 |
| 6429466 | Integrated circuit substrate that accommodates lattice mismatch stress A method for growing a crystalline layer that includes a first material on a growth surface of a crystalline substrate of a second material, wherein the first material and the second material have different lattice constants. A buried layer is generated i... | 08/06/2002 |
| 6423590 | High voltage transistor using P+ buried layer A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This... | 07/23/2002 |
| 6423603 | Method of forming a microwave array transistor for low-noise and high-power applications A transistor array including a plurality of transistors. Each transistor includes an emitter. An emitter region contact overlies each emitter region. At least one base region underlies each emitter region and is common to a plurality of transistors in the... | 07/23/2002 |
| 6417536 | Semiconductor device with memory capacitor having an electrode of Si1-x Gex A semiconductor device with a semiconductor body (1) provided with a memory capacitor (12, 26) with a lower electrode (11, 23) consisting of a layer of semiconductor material (7, 23) having a rough surface (8, 24) formed by hemispherical grains (9, 25) of... | 07/09/2002 |
| 6387768 | Method of manufacturing a semiconductor component and semiconductor component thereof A method of manufacturing a semiconductor component includes providing a substrate (110), an electrically insulative layer (710 or 810) over the substrate, and an electrically conductive layer (820) over the electrically insulative layer. A hole (1510) is... | 05/14/2002 |
| 6383885 | Bipolar transistor with improved reverse breakdown characteristics A bipolar transistor (10) in an IC includes a semiconductor wafer defining a collector area (14) with a first conductivity type, a base area (20) with a second conductivity type formed in the collector area (14), and an emitter formed in the base area. A ... | 05/07/2002 |
| 6376322 | Base-emitter region of a submicronic bipolar transistor The present invention relates to a method of manufacturing the base and emitter regions of a bipolar transistor, including the steps of depositing a first heavily-doped P-type polysilicon layer; eliminating the first polysilicon layer in its central porti... | 04/23/2002 |
| 6368929 | Method of manufacturing a semiconductor component and semiconductor component thereof A method of manufacturing a semiconductor component and the component thereof includes forming a dielectric layer (620) over a portion of a passivation ledge (640) in an emitter layer (280) and overlapping a base contact (660) onto the dielectric layer (6... | 04/09/2002 |
| 6365918 | Method and device for interconnected radio frequency power SiC field effect transistors The present invention relates to a method and device for interconnecting radio frequency power SiC field effect transistors. To improve the parasitic source inductance advantage is taken of the small size of the transistors, wherein the bonding pads are p... | 04/02/2002 |
| 6358807 | Bipolar semiconductor device and method of forming same having reduced transient enhanced diffusion A BiCMOS semiconductor device and a method of forming same are disclosed. A bipolar transistor region is formed adjacent a CMOS device region within a semiconductor substrate. Carbon is implanted in an amount ranging from about 1013 to about 10... | 03/19/2002 |
| 6352901 | Method of fabricating a bipolar junction transistor using multiple selectively implanted collector regions A process for fabricating a bipolar junction transistor, featuring the use of multiple self-aligned collector regions, used to limit the width of the base region of the transistor, has been developed. The self-aligned collector regions are formed via mult... | 03/05/2002 |
| 6346453 | Method of producing a SI-GE base heterojunction bipolar device A method of producing a bipolar transistor includes the step of providing a sacrificial mesa over a layer of SiGe in order to prevent a polysilicon covering layer from forming over a predetermined region of the SiGe layer forming the transistor base. Afte... | 02/12/2002 |
| 6340618 | RF power transistor A method for manufacturing a silicon bipolar power high frequency transistor device is disclosed. A transistor device according to the present method is also disclosed. The transistor device assures conditions for maintaining a proper BVCER to avoid colle... | 01/22/2002 |
| 6339248 | Optimized floating P+ region photodiode for a CMOS image sensor A photodiode with an optimized floating P+ region for a CMOS image sensor. The photodiode is constructed with a P+/Nwell/Psub structure. The Nwell/Psub junction of the photodiode acts as a deep junction photodiode which offers high sensitivity. The P+ flo... | 01/15/2002 |
| 6337251 | Method of manufacturing semiconductor device with no parasitic barrier In a method of manufacturing a semiconductor device, a first insulating film is formed on a semiconductor substrate, a first conductive film is formed on the first insulating film, and a second insulating film is formed on the first conductive film. An op... | 01/08/2002 |
| 6333235 | Method for forming SiGe bipolar transistor A method for fabricating bipolar transistor frequently used in high frequency circuit is disclosed herein. The foregoing method includes the following steps. First, a first oxide layer is formed on a p-type substrate, followed by developing a first photor... | 12/25/2001 |
| 6333216 | Method in the manufacturing of a semiconductor device A selective etching method in the fabrication of a semiconductor device is provided. The method involves the steps of: depositing an amorphous layer of semiconductor material on a monocrystalline substrate of the same semiconductor material; depositing at... | 12/25/2001 |
| 6329259 | Collector-up RF power transistor A method for manufacturing a low voltage high frequency silicon power transistor applying epitaxial mesa structure using a minimized number of masks has a highly doped silicon n++ substrate forming the emitter. Also a low voltage high frequency... | 12/11/2001 |
| 6320212 | Superlattice fabrication for InAs/GaSb/AISb semiconductor structures A semiconductor structure and a method of forming same is disclosed. The method includes forming, on a substrate, an n-doped collector structure of InAs/AlSb materials; forming a base structure on said collector structure which base structure comprises p-... | 11/20/2001 |
| 6316324 | Method of manufacturing semiconductor device without forming selective region by lithography A method of manufacturing a semiconductor device includes the step of doping an N-type impurity via a selective region formed on a semiconductor substrate by lithography, the step of doping a P-type impurity in the semiconductor substrate subsequent to th... | 11/13/2001 |
| 6313000 | Process for formation of vertically isolated bipolar transistor device A vertically-isolated bipolar transistor occupying reduced surface area is fabricated by circumscribing an expected active device region within a first narrow trench. The first trench is filled with sacrificial material impermeable to diffusion of conduct... | 11/06/2001 |
| 6310368 | Semiconductor device and method for fabricating same A semiconductor device includes: a semiconductor layered structure including a predetermined mesa portion, formed on a semiconductor substrate; a support member formed so as to bury the mesa portion; and an interconnection layer formed on a top surface of... | 10/30/2001 |
| 6306695 | Modified source side inserted anti-type diffusion ESD protection device An ESD protection circuit that will prevent internal circuits of an integrated circuit is formed on a semiconductor substrate to prevent damage during extreme voltage levels from an ESD voltage source and is connected to an input/output pad. A plurality o... | 10/23/2001 |
| 6303420 | Integrated bipolar junction transistor for mixed signal circuits A method for forming integrated circuit bipolar junction transistors for mixed signal circuits. The implants used to form the well regions of the CMOS circuits 20, 40 form the collector regions of bipolar junction transistors. The CMOS transistor pocket i... | 10/16/2001 |
| 6297119 | Semiconductor device and its manufacture The present invention discloses a semiconductor device having a PNP bipolar transistor and an NPN bipolar transistor having excellent transistor characteristics formed on the same semiconductor substrate, and a method of manufacturing the semiconductor de... | 10/02/2001 |
| 6297118 | Vertical bipolar semiconductor power transistor with an interdigitzed geometry, with optimization of the base-to-emitter potential difference A transistor including an epitaxial layer with a first conductivity type, a base buried region with a second conductivity type, and a sinker base region with the second conductivity type which extends from a main surface of the transistor to the base buri... | 10/02/2001 |
| 6281089 | Method for fabricating an embedded flash memory cell A method for embedded flash cell fabrication beyond 0.35 .XI.m generation. First, a relatively thick field oxide layer is formed on the P-type substrate to separate the flash cell areas and logic cell area. The flash cell areas are divided into tunnel oxi... | 08/28/2001 |
| 6274451 | Method of fabricating a gate-control electrode for an IGBT transistor This method of fabricating a gate-control electrode (28) for an insulated-gate bipolar transistor, from a plate of electrically conducting material which is covered with an electrically insulating layer (22) and, on one of its large faces, delimits a conn... | 08/14/2001 |
| 6265276 | Structure and fabrication of bipolar transistor A complementary bipolar transistor device, made of two separate conductive films such as two highly doped polysilicon films of opposite conductivity types. The doped polysilicon film is used for a base of NPN transistor and an emitter of a PNP transistor ... | 07/24/2001 |
| 6265275 | Method of selectively doping the intrinsic collector of a vertical bipolar transistor with epitaxial base The collector of a vertical bipolar transistor is selectively doped by a first implantation of dopants before the epitaxy of the base, and is selectivly doped by a second implantation of dopants through the epitaxial base. Two implanted zones with differe... | 07/24/2001 |
| 6258685 | Method of manufacturing hetero-junction bipolar transistor A method of manufacturing a hetero-junction bipolar transistor including a carbon-doped base layer includes the steps of (a) growing a base layer on an underlying layer through chemical vapor deposition, (b) forming at least one semiconductor layer over t... | 07/10/2001 |
| 6255183 | Manufacture of a semiconductor device with a MOS transistor having an LDD structure using SiGe spacers A method of manufacturing a semiconductor device with a MOS transistor having an LDD structure. A gate dielectric (6) and a gate electrode (7, 8) are formed on a surface (5) of a silicon substrate (1). The surface adjacent the gate electrode is then expos... | 07/03/2001 |
| 6242313 | Use of polysilicon field plates to improve high voltage bipolar device breakdown voltage A method for fabricating a buried layer pinched collector bipolar, (BPCB), device, sharing several process steps with simultaneously formed CMOS devices, has been developed. The BPCB device fabrication sequence features the use of polysilicon field plates... | 06/05/2001 |
| 6232193 | Method of forming isolated integrated injection logic gate An integrated injection logic device is provided in which each collector of an I2L gate is isolated by a field oxide ("FOX"), or by other suitable isolation such as, for example, an isolation trench. The connection of the base to the collectors, between t... | 05/15/2001 |
| 6228733 | Non-selective epitaxial depostion technology Base layer formation without the use of selective epitaxial deposition is described. The process begins with the deposition of a seed layer of polysilicon over both the field oxide and the wafer surface that lies between them. An opening in said seed laye... | 05/08/2001 |
| 6225179 | Semiconductor integrated bi-MOS circuit having isolating regions different in thickness between bipolar area and MOS area and process of fabrication thereof A bi-MOS circuit is fabricated on first active regions assigned to the bipolar transistor and on second active regions assigned to the field effect transistors, and the field effect transistors are fabricated after said bipolar transistor, because a high-... | 05/01/2001 |
| 6218254 | Method of fabricating a self-aligned bipolar junction transistor in silicon carbide and resulting devices A method of fabricating a self-aligned bipolar junction transistor in a semiconductor structure having a first layer of silicon carbide generally having a first conductivity type and a second layer of silicon carbide generally having a second conductivity... | 04/17/2001 |
