Bizarre Patents
Combination Beverage Container and Spittoon
A combination beverage container and spittoon includes a bottom portion including outer wall and a first inner wall defining a spittoon space.
PatentStorm News
Make the Most of PatentStorm
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest patents by subscribing to an RSS feed.
Got questions? Ask a Patent Expert!
Registered users: Manage your profile, comments and alerts.
| Number | Title | Issue Date |
| 7674681 | Semiconductor device and method for manufacturing the same Disclosed are a semiconductor device and a method for manufacturing the same. The semiconductor device includes a semiconductor substrate including first and second well areas doped with second conductive ions, a third well area in the first well and doped with the ... | 03/09/2010 |
| 7666749 | SiGe semiconductor device and method of manufacturing the same Provided are a SiGe semiconductor device and a method of manufacturing the same. The method includes the steps of: forming a buried collector by doping impurity ions into a buried collector region formed on a substrate; forming a collector layer which is an active r... | 02/23/2010 |
| 7638404 | Method for forming low temperature polysilicon thin film transistor with low doped drain structure A method for forming a low temperature polysilicon thin film transistor with a low doped drain structure comprises: a) forming a polysilicon island on a substrate; b) forming a dielectric layer, a metal layer and a cap layer in sequence cover to the polysilicon isla... | 12/29/2009 |
| 7622357 | Semiconductor device structures with backside contacts for improved heat dissipation and reduced parasitic resistance The present invention relates to a device structure that comprises a substrate with front and back surfaces, and at least one semiconductor device with a first conductive structure located in the substrate and a second conductive structure located thereover. A first... | 11/24/2009 |
| 7618871 | Method for the production of a bipolar transistor comprising an improved base terminal For the production of an improved bipolar transistor comprising a low-resistance base terminal, a dielectric layer is deposited over the semiconductor substrate and is highly doped via an implantation mask. In a subsequent controlled thermal step, the dopant is then... | 11/17/2009 |
| 7615455 | Integrated circuit bipolar transistor A bipolar transistor having a base region resting by its lower surface on a collector region and surrounded with a first insulating layer, a base contact conductive region in contact with an external upper peripheral region of the base region, a second insulating re... | 11/10/2009 |
| 7611953 | Bipolar transistor with isolation and direct contacts A bipolar transistor has a collector that is contacted directly beneath a base-collector junction by metallization to reduce collector resistance. A conventional reach-through and buried layer, as well as their associated resistance, are eliminated. The transistor i... | 11/03/2009 |
| 7605046 | Active matrix structure for a display device and method for its manufacture The invention relates to an active matrix structure and method for manufacturing the active matrix structure for a display device, wherein the structure includes: providing a matrix substrate with a number of row lines and a number of column lines, with each point o... | 10/20/2009 |
| 7595249 | Bipolar transistors with vertical structures A method for fabricating a bipolar transistor includes forming a vertical sequence of semiconductor layers, forming an implant mask on the last formed semiconductor layer, and implanting dopant ions into a portion of one or more of the semiconductor layers. The sequ... | 09/29/2009 |
| 7541248 | Integrated semiconductor device and method of manufacturing thereof An integrated semiconductor device containing semiconductor elements that have respective desired on-resistances and breakdown voltages achieves appropriate characteristics as a whole of the integrated semiconductor element. The integrated semiconductor device inclu... | 06/02/2009 |
| 7521327 | High f and fbipolar transistor and method of making same A high fT and fmax bipolar transistor includes an emitter, a base, and a collector. The emitter has a lower portion and an upper portion that extends beyond the lower portion. The base includes an intrinsic base and an extrinsic base. The intri... | 04/21/2009 |
| 7517768 | Method for fabricating a heterojunction bipolar transistor A bipolar transistor with a SiGe:C film and a seed layer forming beneath the SiGe:C film and methods of making same. The method includes placing a substrate in a reactor chamber and introducing a silicon source gas into the reactor chamber to form a silicon seed lay... | 04/14/2009 |
| 7494887 | Method and apparatus for fabricating heterojunction bipolar transistors with simultaneous low base resistance and short base transit time A method for fabricating heterojunction bipolar transistors that exhibit simultaneous low base resistance and short base transit times, which translate into semiconductor devices with low power consumption and fast switching times, is presented. The method comprises... | 02/24/2009 |
| 7488662 | Self-aligned vertical PNP transistor for high performance SiGe CBiCMOS process A structure and a process for a self-aligned vertical PNP transistor for high performance SiGe CBiCMOS process. Embodiments include SiGe CBiCMOS with high-performance SiGe NPN transistors and PNP transistors. As the PNP transistors and NPN transistors contained diff... | 02/10/2009 |
| 7485537 | Method of fabricating a vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for SOI BiCMOS with reduced buried oxide thickness The present invention provides a a method of fabricating bipolar junction transistors (BJTs) on selected areas of a very thin buried oxide (BOX) using a conventional silicon-on-insulator (SOI) starting wafer with a thick BOX. The reduced BOX thickness underneath the... | 02/03/2009 |
| 7473609 | Surface treatment in preparation for contact placement A contact is formed on indium-phosphide material. Regions of the indium-phosphide material are exposed. An energetic bombardment is performed on exposed regions of the indium-phosphide material. Metal is deposited on the exposed regions of the indium-phosphide mater... | 01/06/2009 |
| 7473610 | Local collector implant structure for heterojunction bipolar transistors and method of forming the same A method of forming a heterojunction bipolar transistor (HBT) device is disclosed. The method includes forming an intrinsic base layer over a collector layer; forming a sacrificial block structure over the intrinsic base layer; formina a sacrificial spacer layer sur... | 01/06/2009 |
| 7470594 | System and method for controlling the formation of an interfacial oxide layer in a polysilicon emitter transistor A method is disclosed for controlling the formation of an interfacial oxide layer in a polysilicon emitter transistor device. The interfacial oxide layer is formed between an underlying substrate of single crystal silicon and an upper layer of polysilicon. The curre... | 12/30/2008 |
| 7462546 | Collector tailored structures for integration of binary junction transistors A bipolar transistor is formed in an integrated BiCMOS process. A buried layer is formed in a semiconductor body. An intrinsic dilute mask is formed over the buried layer that covers at least a portion of a selected region of a target deep well region. The intrinsic... | 12/09/2008 |
| 7459367 | Method of forming a vertical P-N junction device A P-N junction device and method of forming the same are disclosed. The P-N junction device may include a P-N diode, a PiN diode or a thyristor. The P-N junction device may have a monocrystalline or polycrystalline raised anode. In one embodiment, the P-N junction d... | 12/02/2008 |
| 7459368 | Method for manufacturing integrated circuits having silicon-germanium heterobipolar transistors Method for manufacturing integrated circuits having silicon-germanium heterobipolar transistors, wherein a collector semiconductor region is created, an etch stop layer is created on a connection region, an opening is introduced into this etch stop layer, semiconduc... | 12/02/2008 |
| 7449388 | Method for forming multiple doping level bipolar junctions transistors A process for forming bipolar junction transistors having a plurality of different collector doping densities on a semiconductor substrate and an integrated circuit comprising bipolar junction transistors having a plurality of different collector doping densities. A... | 11/11/2008 |
| 7446009 | Manufacturing method for semiconductor device A semiconductor device manufacturing method including forming a conductive layer and a silicon film on a semiconductor substrate including an active region, forming an emitter electrode containing a first impurity on the silicon film above the active region, partial... | 11/04/2008 |
| 7442616 | Method of manufacturing a bipolar transistor and bipolar transistor thereof A bipolar transistor (100) is manufactured using the following processes: (a) forming a base electrode layer (129) as a portion of a base electrode over a semiconductor substrate (110); (b) forming a first portion of an emitter electrode (154... | 10/28/2008 |
| 7442617 | Method for manufacturing bipolar transistor A method for manufacturing a bipolar transistor comprising: forming a device isolation layer in a device isolation region of a semiconductor substrate having therein first and second well regions having a first conductivity; implanting ions of a second conductivity ... | 10/28/2008 |
| 7439608 | Symmetric bipolar junction transistor design for deep sub-micron fabrication processes Described herein are embodiments of a bipolar junction transistor including a plurality of base terminal rings having an emitter terminal ring between any two base terminal rings of the plurality of base terminal rings, and a collector terminal ring surrounding the ... | 10/21/2008 |
| 7432169 | Method for manufacturing semiconductor device An excessive etch in the conventional manufacturing process causes a roughened surface of a contact bottom, resulting in an increased variation in characteristics of semiconductor devices. A bipolar transistor having a collector region 4 provided in a bottom ... | 10/07/2008 |
| 7422952 | Method of forming a BJT with ESD self protection A ballasting region is placed between the base region and the collector contact of a bipolar junction transistor to relocate a hot spot away from the collector contact of the transistor. Relocating the hot spot away from the collector contact prevents the collector ... | 09/09/2008 |
| 7422951 | Method of fabricating self-aligned bipolar transistor The present invention provides a method of fabricating a self-aligned bipolar transistor, by which the fabricating method can be simplified by forming P+ and N+ junctions by self-alignment and by which device reliability can be enhanced. The present invention includ... | 09/09/2008 |
| 7414298 | Super self-aligned collector device for mono-and hetero bipolar junction transistors, and method of making same The invention relates to a process of forming a compact bipolar junction transistor (BJT) that includes forming a self-aligned collector tap adjacent the emitter stack and an isolation structure. A base layer is formed from epitaxial silicon that is disposed in the ... | 08/19/2008 |
| 7390720 | Local collector implant structure for heterojunction bipolar transistors and method of forming the same A bipolar transistor structure includes an intrinsic base layer formed over a collector layer, an emitter formed over the intrinsic base layer, and an extrinsic base layer formed over the intrinsic layer and adjacent the emitter. A ring shaped collector implant stru... | 06/24/2008 |
| 7387918 | Method of forming a silicon controlled rectifier structure with improved punch through resistance When a high-voltage, such as from an ESD pulse, is placed across a silicon controlled rectifier, which includes an NPN transistor and a PNP transistor that is connected to the NPN transistor, the likelihood of punch through occurring between two regions of the recti... | 06/17/2008 |
| 7371650 | Method for producing a transistor structure A method for fabricating a transistor structure with a first and a second bipolar transistor having different collector widths is presented. The method includes providing a semiconductor substrate, introducing a first buried layer of the first bipolar transistor and... | 05/13/2008 |
| 7361996 | Semiconductor device having tin-based solder layer and method for manufacturing the same A semiconductor device includes: a semiconductor substrate; a base member; a tin-based solder layer; a first metal layer; and a first alloy layer. The semiconductor substrate is bonded to the base member through the first metal layer, the first alloy layer and the t... | 04/22/2008 |
| 7358152 | Wafer bonding of thinned electronic materials and circuits to high performance substrate A method of bonding a wafer to a substrate comprising the steps of: providing a wafer having a front surface and a back surface; attaching the front surface of the wafer to a support; thinning the wafer from the back surface; bonding the back surface of the wafer to... | 04/15/2008 |
| 7354840 | Method for opto-electronic integration on a SOI substrate According to an exemplary embodiment, a method includes providing a silicon-on-insulator substrate including a buried oxide layer situated over a bulk silicon substrate and a silicon layer situated over the buried oxide layer. A trench is formed in the silicon layer... | 04/08/2008 |
| 7348671 | Vias having varying diameters and fills for use with a semiconductor device and methods of forming semiconductor device structures including same A method for forming electrical interconnects having different diameters and filler materials through a semiconductor wafer comprises forming first and second openings through a semiconductor, wherein the first opening has a narrower width (smaller diameter) than th... | 03/25/2008 |
| 7341920 | Method for forming a bipolar transistor device with self-aligned raised extrinsic base Disclosed are embodiments of a method of fabricating a bipolar transistor with a self-aligned raised extrinsic base. In the method a dielectric pad is formed on a substrate with a minimum dimension capable of being produced using current state-of-the-art lithographi... | 03/11/2008 |
| 7342293 | Bipolar junction transistors (BJTS) with second shallow trench isolation (STI) regions, and methods for forming same The present invention relates to bipolar junction transistors (BJTS). The collector region of each BJT is located in a semiconductor substrate surface and adjacent to a first shallow trench isolation (STI) region. A second STI region is provided, which extends betwe... | 03/11/2008 |
| 7338848 | Method for opto-electronic integration on a SOI substrate and related structure According to an exemplary embodiment, a method includes providing a silicon-on-insulator substrate including a buried oxide layer situated over a bulk silicon substrate and a silicon layer situated over the buried oxide layer. A trench is formed in the silicon layer... | 03/04/2008 |