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...that to encourage use of his new invention, the shopping cart, market owner Sylvan Goldman hired fake shoppers to push the carts around his store in Oklahoma City? Seems his customers were reluctant to give up their hand-carried baskets.
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| Number | Title | Issue Date |
| 5599728 | Method of fabricating a self-aligned high speed MOSFET device A high speed MOSFET device includes a punchthrough stopper region in the channel of the device formed by high energy ion implantation through the gate electrode and self-aligned therewith. The device has reduced capacitance. A self-aligned recessed channe... | 02/04/1997 |
| 5585294 | Method of fabricating lateral double diffused MOS (LDMOS) transistors A process for the fabrication of an improved LDMOS transistor, and such an improved LDMOS transistor are provided. The improved LDMOS transistor is in a semiconductor layer of a first conductivity type. The transistor has a source and drain of a second co... | 12/17/1996 |
| 5583064 | Semiconductor device and process for formation thereof A recess is formed (dug) into the surface of a substrate to form a gate channel in the recess, so that a monocrystalline source/drain region can be formed at a level higher than that of the channel. The process includes the steps of: (a) forming an insula... | 12/10/1996 |
| 5580799 | Method of manufacturing transistor with channel implant A semiconductor device includes a substrate having a first conduction type. A gate insulating film is provided on the substrate. A gate electrode is formed on the gate insulating film. A source region provided on the substrate has a second conduction type... | 12/03/1996 |
| 5578509 | Method of making a field effect transistor A method for producing a field effect transistor including source and drain regions produced by implanting a dopant impurity employing a gate electrode as a mask includes producing a gate electrode at a region on a first conductivity type semiconductor su... | 11/26/1996 |
| 5569616 | Process for forming an output circuit device for a charge transfer element having tripartite diffusion layer An output circuit device for detecting and converting signal charge transferred thereto from a charge transfer section of a CCD into a signal voltage and a method of forming same. A first diffusion region is formed by diffusing into the semiconductor body... | 10/29/1996 |
| 5569615 | Method for forming a flash memory by forming shallow and deep regions adjacent the gate A laser doping process comprising: irradiating a laser beam operated in a pulsed mode to a single crystal semiconductor substrate of a first conductive type in an atmosphere of an impurity gas which imparts the semiconductor substrate a conductive type op... | 10/29/1996 |
| 5565369 | Method of making retarded DDD (double diffused drain) device structure A method of forming a retarded double diffused drain structure, and the resultant retarded double diffused drain structure, for a field effect transistor are described. A silicon substrate with field isolation regions and a gate structure is provided. A l... | 10/15/1996 |
| 5550069 | Method for producing a PMOS transistor A method for producing a PMOS transistor. A p doped substrate and an n doped trough are provided by implantation and subsequent diffusion. The transistor is insulated by means of a field oxide layer. The transistor gates are produced using a photolithogra... | 08/27/1996 |
| 5541132 | Insulated gate semiconductor device and method of manufacture An insulated gate field effect transistor (10) having an reduced gate to drain capacitance and a method of manufacturing the field effect transistor (10). A dopant well (13) is formed in a semiconductor material (11). A gate oxide layer (26) is formed on ... | 07/30/1996 |
| 5538913 | Process for fabricating MOS transistors having full-overlap lightly-doped drain structure A process for fabricating a MOS transistor having a full-overlap lightly-doped drain is disclosed. The MOS transistor is fabricated on a semiconductor silicon substrate that has formed thereon a field oxide layer that defines the active region of the MOS ... | 07/23/1996 |
| 5538909 | Method of making a shallow trench large-angle-tilt implanted drain device The present invention provides a novel MOS transistor structure and method of fabrication. To make this device, a gate electrode is formed on a silicon substrate first and a pair of shallow trenches with a depth of between 200Å to 500Å are formed apart ... | 07/23/1996 |
| 5527719 | Process for making a semiconductor MOS transistor using a fluid material A process for formation of an MOS semiconductor device having an LDD structure is disclosed, which may include the steps of: forming an active region and an isolation region on a semiconductor substrate; forming a first insulating layer on the surface of ... | 06/18/1996 |
| 5518945 | Method of making a diffused lightly doped drain device with built in etch stop A method of fabricating a lightly doped drain MOSFET device with a built in etch stop is disclosed. After forming a gate electrode on a substrate through conventional methods, a conformal doped layer is deposited on the gate electrode. A conformal layer o... | 05/21/1996 |
| 5512506 | Lightly doped drain profile optimization with high energy implants After growth of a thin oxide on a silicon semiconductor body, and formation of a gate thereover, a blanket layer of oxide is deposited over the resulting structure, this oxide layer having, as measured from the surface of the silicon body, relatively thic... | 04/30/1996 |
| 5486482 | Process for fabricating metal-gate CMOS transistor A process for fabricating metal-gate CMOS transistors on a semiconductor substrate having a well region therein is disclosed herein. The process comprises the steps of: First forming a shielding layer with designated patterns on the substrate and the well... | 01/23/1996 |
| 5482878 | Method for fabricating insulated gate field effect transistor having subthreshold swing Insulated gate field effect transistors (10, 70) having process steps for setting the VT and a device leakage current which are decoupled from the process steps for providing punchthrough protection, thereby lowering a subthreshold swing. In a ... | 01/09/1996 |
| 5476802 | Method for forming an insulated gate field effect transistor A method for forming an insulated gate field effect transistor capable of providing shorter channel lengths, said process comprising: forming on an insulator film having provided on a semiconductor, a portion for establishing a gate therewith in the later step... | 12/19/1995 |
| 5472899 | Process for fabrication of an SRAM cell having a highly doped storage node An SRAM cell and a process for forming an SRAM cell comprises: forming a gate oxide layer on a semiconductor substrate, forming a gate on the gate oxide layer, forming a first ion implantation into the substrate in areas adjacent to the gate, performing a... | 12/05/1995 |
| 5464784 | Method of fabricating integrated devices A method comprising the steps of depositing a first and second polysilicon layer, separated by an oxide layer; selectively etching the second polysilicon layer to form first gate regions; forming first substrate regions in the substrate and laterally in r... | 11/07/1995 |
| 5462884 | Method of making field effect transistor with T-shaped gate electrode A semiconductor device with a small gate-source capacitance is fabricated by disposing a semiconductor epitaxial layer of one conductivity type on a substrate. Two metal layers which, when subjected to etching by a selected etchant, are etched at differen... | 10/31/1995 |
| 5460986 | Process for making a power MOSFET device and structure A method for making a stable low threshold voltage p-channel power MOSFET device having a p-type gate layer (14) includes incorporating a p-type dopant into the gate layer (14) formed over a gate oxide layer (13). The p-type dopant is incorporated within ... | 10/24/1995 |
| 5451533 | Bidirectional blocking lateral MOSFET with improved on-resistance A bidirectional current blocking lateral power MOSFET including a source and a drain which are not shorted to a substrate, and voltages that are applied to the source and drain are both higher than the voltage at which the body is maintained (for an N-cha... | 09/19/1995 |
| 5439831 | Low junction leakage MOSFETs Shallow junction field effect transistors are made by a low temperature process comprising ion implanting source/drain regions through a buffer layer in two steps, the first an ion implant at high dosage and low energy and the second an ion implant at low... | 08/08/1995 |
| 5438007 | Method of fabricating field effect transistor having polycrystalline silicon gate junction A field effect transistor includes a polycrystalline silicon gate having a semiconductor junction therein. The semiconductor junction is formed of first and second oppositely doped polycrystalline silicon layers, and extends parallel to the substrate face... | 08/01/1995 |
| 5436178 | Method of making semiconductor device including MOS type field effect transistor A semiconductor device includes an MOS field effect transistor having a structure in which the tops of its source/drain regions are covered with a polycrystalline silicon layer. The impurity concentration distribution in its depth direction of the source/... | 07/25/1995 |
| 5424229 | Method for manufacturing MOSFET having an LDD structure A dielectric film, such as a silicon nitride film, is formed on a p type silicon substrate. An opening is formed in the silicon nitride film. With the silicon nitride film used as a mask, a phosphorns ion is implanted into the surface portion of the subst... | 06/13/1995 |
| 5397715 | MOS transistor having increased gate-drain capacitance A process is described for providing a self-aligned MOS transistor having a selectable gate-drain capacitance. In a self-aligned process for forming a PMOS transistor, a polysilicon layer is etched to expose portions of an n-type substrate in which it is ... | 03/14/1995 |
| 5395772 | SOI type MOS transistor device An SOIMOS transistor device which comprises a substrate, an insulating film formed on the substrate, a source and a drain sandwiching a channel region therebetween and formed on the insulating film is described. The channel region has regions in contact w... | 03/07/1995 |
| 5376570 | Transistor having a nonuniform doping channel and method for fabricating the same An MOSFET having a nonuniform doping channel and a method for fabricating the same. The MOS transistor having a nonuniform doping channel is comprised of: a gate oxide film formed on a semiconductor substrate provided with a trench; a gate electrode of so... | 12/27/1994 |
| 5371024 | Semiconductor device and process for manufacturing the same A semiconductor device has a semiconductor substrate of the first conductivity type, a gate electrode buried in a groove formed in an element region of the substrate, first source and drain regions of the second conductivity type formed in surface regions... | 12/06/1994 |
| 5346836 | Process for forming low resistance contacts between silicide areas and upper level polysilicon interconnects A process for forming low resistance contacts between silicide areas and upper level polysilicon interconnect layers including a specific doping technique that provides solid low resistance contacts between a lower level of a silicided area and an upper l... | 09/13/1994 |
| 5342798 | Method for selective salicidation of source/drain regions of a transistor Selective salicidation of source/drain regions of a transistor is accomplished by performing an implant into a first plurality of transistor source/drain regions on an integrated circuit. As a result of the implant, doping density of the first plurality o... | 08/30/1994 |
| 5338960 | Formation of dual polarity source/drain extensions in lateral complementary channel MOS architectures Dual polarity source/drain extensions are formed simultaneously in both PMOS and NMOS devices of a CMOS architecture using a common set of implants, so to be contiguous with one or both of source and drain regions of both the PMOS and the NMOS structures.... | 08/16/1994 |
| 5326713 | Buried contact process A method of forming a buried contact to a source/drain junction or other active device region in a silicon substrate. A silicon oxide layer is formed over the silicon substrate. A first polysilicon layer is formed over the silicon oxide layer. A resist ma... | 07/05/1994 |
| 5292676 | Self-aligned low resistance buried contact process A buried contact is formed in a substrate implantation of phosphorous or arsenic through a window cut into the insulating silicon oxide layer and a superimposed thin silicon layer. The photoresist used to etch the window is cut back a limited amount prior... | 03/08/1994 |
| 5290728 | Method for producing a semiconductor device A method for fabricating a semiconductor device including a contact window formed in an interlevel insulator so as to connect electrodes to an interconnection and to connect impurity diffusion regions to the interconnection is provided. After forming an i... | 03/01/1994 |
| 5272099 | Fabrication of transistor contacts The method of forming an integrated circuit field effect transistor having a gate electrode, source and drain elements with buried contacts to a silicon substrate. A gate silicon oxide layer is formed on the silicon substrate. An in-situ doped layer of po... | 12/21/1993 |
| 5246872 | Electrostatic discharge protection device and a method for simultaneously forming MOS devices with both lightly doped and non lightly doped source and drain regions An electrostatic discharge protection circuit having a non-lightly doped drain MOS device for protecting other lightly doped drain devices on an integrated circuit, and a method of concurrently fabricating both the non lightly doped and lightly doped devi... | 09/21/1993 |
| 5242841 | Method of making LDMOS transistor with self-aligned source/backgate and photo-aligned gate An embodiment of the present invention is a method of fabricating power and non-power devices on a semiconductor substrate, the method comprising: forming alignment marks in the substrate (100); introducing a dopant of a first conductivity type into the s... | 09/07/1993 |
