Class 438/306 - Plural doping steps

Subclass of Class 438 - Semiconductor device manufacturing: process
Definition: Process including multiple steps of introducing dopant species
No. of patents: 585
Last issue date: 01/03/2012

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Number	Title	Issue Date
8088666	Semiconductor device manufacture method including process of implanting impurity into gate electrode independently from source/drain and semiconductor device manufactured by the method A gate electrode made of semiconductor is formed on the partial surface area of a semiconductor substrate. A mask member is formed on the surface of the semiconductor substrate in an area adjacent to the gate electrode. Impurities are implanted into the gate electro...	01/03/2012
8058134	Junction profile engineering using staged thermal annealing An annealing method includes performing an activation annealing on a wafer with a peak temperature of greater than about 1200° C., wherein the activation annealing has a first duration; and performing a defect-recovery annealing on the wafer at a defect-recovery te...	11/15/2011
8053325	Body contact structures and methods of manufacturing the same A body contact structure which reduce parasitic capacitance and improves body resistance of a device and methods of manufacture. The method includes forming a gate insulator material and gate electrode material on a substrate. The method further includes patterning ...	11/08/2011
8008158	Dopant implantation method using multi-step implants A method of forming a dopant implant region in a MOS transistor device having a dopant profile having a target dopant concentration includes implanting a first concentration of dopants into a region of a substrate, where the first concentration of dopants is less th...	08/30/2011
7977199	Method for measuring dopant concentration during plasma ion implantation Embodiments of the invention generally provide methods for end point detection at predetermined dopant concentrations during plasma doping processes. In one embodiment, a method includes positioning a substrate within a process chamber, generating a plasma above the...	07/12/2011
7968415	Transistor with reduced short channel effects and method A method of fabricating a transistor (10) comprises forming source and drain regions (46) and (47) using a first sidewall (42) and (43) as a mask and forming a deep blanket source and drain regions (54) and (56) using...	06/28/2011
7960239	Power device A power device with improved reliability and a method for producing the same is disclosed. One embodiment provides an active area having an electrical power dissipation characteristic, a metallization layer portion configured with respect to the active area so that ...	06/14/2011
7892933	Semiconductor device and method of manufacturing semiconductor device According to an aspect of an embodiment, a semiconductor device has a semiconductor substrate, a gate insulating film on the semiconductor substrate, a gate electrode formed on the gate insulating film, an impurity diffusion region formed in an area of the semicondu...	02/22/2011
7888223	Method for fabricating P-channel field-effect transistor (FET) A method for fabrication a p-type channel FET includes forming a gate on a substrate. Then, a PAI ion implantation process is performed. Further, a pocket implantation process is conducted to form a pocket region. Thereafter, a first co-implantation process is perfo...	02/15/2011
7858482	Method of forming a semiconductor device using stress memorization A stress memorization technique (SMT) film is deposited over a semiconductor device. The SMT film is annealed with a low thermal budget anneal that is sufficient to create and transfer the stress of the SMT film to the semiconductor device. The SMT film is then remo...	12/28/2010
7851317	Method for fabricating high voltage drift in semiconductor device A drift of a high voltage transistor formed using an STI (shallow trench isolation). The method for forming a high voltage drift of a semiconductor device can include forming a pad insulating film on a semiconductor substrate having a high voltage well; and then ope...	12/14/2010
7785973	Electronic device including a gate electrode having portions with different conductivity types and a process of forming the same An electronic device can include a gate electrode having different portions with different conductivity types. In an embodiment, a process of forming the electronic device can include forming a semiconductor layer over a substrate, wherein the semiconductor layer ha...	08/31/2010
7767535	Semiconductor device and method of manufacturing the same A semiconductor device comprising a semiconductor substrate having a recess whose depth is not more than 6 nm, a source region and a drain region which are formed in a surface region of the semiconductor substrate so as to sandwich the recess, each of the source reg...	08/03/2010
7736984	Method of forming a low resistance semiconductor contact and structure therefor In one embodiment, silicide layers are formed on two oppositely doped adjacent semiconductor regions. A conductor material is formed electrically contacting both of the two silicides. ...	06/15/2010
7696054	Transistor, a transistor arrangement and method thereof A transistor, transistor arrangement and method thereof are provided. The example method may include determining whether a gate width of the transistor has been adjusted; and adjusting a distance between a higher-concentration impurity-doped region of the transistor...	04/13/2010
7691714	Semiconductor device having a dislocation loop located within a boundary created by source/drain regions and a method of manufacture therefor The present invention provides a method for manufacturing a transistor device, a method for manufacturing an integrated circuit, and a transistor device. The method for manufacturing the transistor device, among other steps, includes forming a gate structure over a ...	04/06/2010
7687365	CMOS structure for body ties in ultra-thin SOI (UTSOI) substrates The present invention provides a semiconducting structure including a substrate having an UTSOI region and a bulk-Si region, wherein the UTSOI region and the bulk-Si region have a same crystallographic orientation; an isolation region separating the UTSOI region fro...	03/30/2010
7682918	ESD protection for semiconductor products A process for forming a vertical DMOS device with an ESD protection transistor that is configured for carrying a breakdown current includes the steps of masking a substrate of a first polarity type and forming spaced apart surface isolation regions. An insulated gat...	03/23/2010
7678656	Method of fabricating an enhanced resurf HVPMOS device An HV PMOS device formed on a substrate having an HV well of a first polarity type formed in an epitaxial layer of a second polarity type includes a pair of field oxide regions on the substrate and at least partially over the HV well. Insulated gates are formed on t...	03/16/2010
7618870	Non-uniformly doped high voltage drain-extended transistor and method of manufacture thereof The present invention provides, in one embodiment, a transistor (100). The transistor (100) comprises a doped semiconductor substrate (105) and a gate structure (110) over the semiconductor substrate (105), the gate structure (1...	11/17/2009
7601600	Power semiconductor device and method for manufacturing the same Disclosed are a power semiconductor device and a method for manufacturing the same. The power semiconductor device has a PIP capacitor and an LDMOS transistor, the LDMOS transistor having second and third gate electrodes separate from a first gate electrode, which m...	10/13/2009
7585739	Semiconductor device and method of fabricating the same An extension region is formed by ion implantation under masking by a gate electrode, and then a substance having a diffusion suppressive function over an impurity contained in a source-and-drain is implanted under masking by the gate electrode and a first sidewall s...	09/08/2009
7553733	Isolated LDMOS IC technology A lateral double diffused metal oxide semiconductor (LDMOS) device includes a gate to control the device, a drain coupled to the gate formed in a well of a first type, a source to form a current path with the drain, and a first field oxide region disposed between th...	06/30/2009
7465637	Method for manufacturing semiconductor device A method for manufacturing a semiconductor device comprises the steps of forming a gate trench in a semiconductor substrate, forming a gate insulation film in an inner wall of the gate trench, filling a gate electrode material into at least an inside of the gate tre...	12/16/2008
7446008	Method for fabricating silicide layers for semiconductor device Disclosed is a method for fabricating a semiconductor device. The method can include forming a first barrier pattern to cover a first region of a semiconductor substrate while exposing second and third regions of the semiconductor substrate, forming a first oxide la...	11/04/2008
7442613	Methods of forming an asymmetric field effect transistor A field effect transistor includes a channel region under a gate stack formed on a semiconductor structure. The field effect transistor also includes a drain region formed with a first dopant doping a first side of the channel region, and includes a source region fo...	10/28/2008
7435636	Fabrication of self-aligned gallium arsenide MOSFETs using damascene gate methods A method for fabricating a gallium arsenide MOSFET device is presented. A dummy gate is formed over a gallium arsenide substrate. Source-drain extensions are implanted into the substrate adjacent the dummy gate. Dummy spacers are formed along dummy gate sidewalls an...	10/14/2008
7416950	MOS transistor forming method A method for forming, in a single-crystal semiconductor substrate of a first conductivity type, doped surface regions of the second conductivity type and deeper doped regions of the first conductivity type underlying the surface regions, including the step of negati...	08/26/2008
7408222	Charge trapping device and method of producing the charge trapping device A charge-trapping device includes a field effect transistor, which has source and drain regions. The source and drain regions have a dopant concentration profile, which has a gradient each in a vertical and a lateral direction with respect to a surface of a semicond...	08/05/2008
7405117	Method of fabricating a lateral double-diffused MOSFET (LDMOS) transistor A method of monolithically fabricating a lateral double-diffused MOSFET (LDMOS) transistor having a source, drain, and a gate on a substrate, with a process flow that is compatible with a CMOS process flow, is disclosed. ...	07/29/2008
7402451	Optimized transistor for imager device An imager device that has mitigated dark current leakage and punch-through protection. The transistor associated with the photoconversion device is formed with a single (i.e, one-sided) active area extension region on one side of the transistor gate opposite the pho...	07/22/2008
7402485	Method of forming a semiconductor device A sidewall spacer structure is formed adjacent to a gate structure whereby a material forming an outer surface of the sidewall spacer structure contains nitrogen. Subsequent to its formation the sidewall spacer structure is annealed to harden the sidewall spacer str...	07/22/2008
7396713	Structure and method for forming asymmetrical overlap capacitance in field effect transistors A method for forming asymmetric spacer structures for a semiconductor device includes forming a spacer layer over at least a pair of adjacently spaced gate structures disposed over a semiconductor substrate. The gate structures are spaced such that the spacer layer ...	07/08/2008
7384844	Method of fabricating flash memory device A method of fabricating a flash memory device includes defining a high voltage region and a low voltage region on a substrate. The high voltage region provides an area for one or more first transistors configured to operation at a first voltage, the low voltage regi...	06/10/2008
7364963	Method for fabricating semiconductor device A method for fabricating a semiconductor device is provided. The method includes: implanting impurities onto a substrate by performing an ion implantation process; recessing portions of the substrate to form a plurality of trenches; performing a first thermal proces...	04/29/2008
7361562	Method of manufacturing semiconductor device Provided is a method of manufacturing a semiconductor device capable of forming a thin high-quality gate oxide layer by suppressing occurrence of recoiled oxygen due to ion implanting. The method of manufacturing a semiconductor device includes steps of: removing an...	04/22/2008
7358167	Implantation process in semiconductor fabrication A semiconductor device is formed by performing an amorphizing ion implantation to implant dopants of a first conductivity type into a semiconductor body. The first ion implantation causes a defect area (e.g., end-of-range defects) within the semiconductor body at a ...	04/15/2008
7358168	Ion implantation method for forming a shallow junction A shallow junction that previously would require the use of a low-energy ion implanter can be directly formed by high-energy or middle-energy ion implanters such that the manufacturer need not purchase a new low-energy ion implanter. In one embodiment, an ion-implan...	04/15/2008
7351622	Methods of forming semiconductor device A method of forming a semiconductor device includes forming a three-dimensional structure formed of a semiconductor on a semiconductor substrate, and isotropically doping the three-dimensional structure by performing a plasma doping process using a first source gas ...	04/01/2008
7348264	Plasma doping method A plasma doping method that can control a dose precisely is realized. In-plane uniformity of the dose is improved. It has been found that, if a bias is applied by irradiating B2H6/He plasma onto a silicon substrate, there is a time at which a d...	03/25/2008

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Class 438/306 - Plural doping steps