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| Number | Title | Issue Date |
| 8404551 | Source/drain extension control for advanced transistors A planar transistor with improved performance has a source and a drain on a semiconductor substrate that includes a substantially undoped channel extending between the source and the drain. A gate is positioned over the substantially undoped channel on the substrate... | 03/26/2013 |
| 8389369 | Electronic device including a doped region disposed under and having a higher dopant concentration than a channel region and a process of forming the same An electronic device can include a drain region of a transistor, a channel region of the transistor, and a doped region that is disposed under substantially all of the channel region, is not disposed under substantially all of a heavily doped portion of the drain re... | 03/05/2013 |
| 8357579 | Methods of forming integrated circuits A method of forming an integrated circuit includes forming a gate structure over a substrate. Portions of the substrate are removed to form recesses adjacent to the gate structure. A dopant-rich layer having first type dopants is formed on a sidewall and a bottom of... | 01/22/2013 |
| 8309420 | Fabrication of semiconductor architecture having field-effect transistors especially suitable for analog applications A semiconductor structure is provided with (i) an empty well having relatively little well dopant near the top of the well and (ii) a filled well having considerably more well dopant near the top of the well. Each well is defined by a corresponding body-material reg... | 11/13/2012 |
| 8258035 | Method to improve source/drain parasitics in vertical devices A method for making a transistor is provided which comprises (a) providing a semiconductor structure having a gate (211) overlying a semiconductor layer (203), and having at least one spacer structure (213) disposed adjacent to said gate; (b) re... | 09/04/2012 |
| 7838369 | Fabrication of semiconductor architecture having field-effect transistors especially suitable for analog applications An insulated-gate field-effect transistor (100, 100V, 140, 150, 150V, 160, 170, 170V, 180, 180V, 190, 210, 210W, 220, 220U, 220V, 220W, 380, or 480) is fabricated so as to have a hypoabrupt vertic... | 11/23/2010 |
| 7811892 | Multi-step annealing process A method of fabricating a dielectric layer is described. A substrate is provided, and a dielectric layer is formed over the substrate. The dielectric layer is performed with a nitridation process. The dielectric layer is performed with a first annealing process. A f... | 10/12/2010 |
| 7785971 | Fabrication of complementary field-effect transistors with vertical body-material dopant profiles tailored to alleviate punchthrough and reduce current leakage Fabrication of complementary first and second insulated-gate field-effect transistors (110 or 112 and 120 or 122) from a semiconductor body entails separately introducing (i) three body-material dopants into the body material (50) ... | 08/31/2010 |
| 7645674 | Semiconductor device having an oxide film formed on a semiconductor substrate sidewall of an element region and on a sidewall of a gate electrode A first isolation is formed on a semiconductor substrate, and a first element region is isolated via the first isolation. A first gate insulating film is formed on the first element region, and a first gate electrode is formed on the first gate insulating film. A se... | 01/12/2010 |
| 7595244 | Fabrication of like-polarity insulated-gate field-effect transistors having multiple vertical body dopant concentration maxima and different halo pocket characteristics Fabrication of two differently configured like-polarity insulated-gate field-effect transistors (40 or 42 and 240 or 242) entails introducing multiple body-material semiconductor dopants of the same conductivity type into a semiconductor ... | 09/29/2009 |
| 7491613 | Line element and method of manufacturing the line element An element capable of manufacturing various devices of any shape having plasticity or flexibility without being limited by shape and a method for manufacturing thereof are provided. An element characterized by that a circuit element is formed continuously or intermi... | 02/17/2009 |
| 7432164 | Semiconductor device comprising a transistor having a counter-doped channel region and method for forming the same A method for making a semiconductor device includes providing a first substrate region and a second substrate region, wherein at least a part of the first substrate region has a first conductivity type and at least a part of the second substrate region has a second ... | 10/07/2008 |
| 7422948 | Threshold voltage adjustment for long channel transistors A threshold voltage adjusted long-channel transistor fabricated according to short-channel transistor processes is described. The threshold-adjusted transistor includes a substrate with spaced-apart source and drain regions formed in the substrate and a channel regi... | 09/09/2008 |
| 7405129 | Device comprising doped nano-component and method of forming the device A device comprising a doped semiconductor nano-component and a method of forming the device are disclosed. The nano-component is one of a nanotube, nanowire or a nanocrystal film, which may be doped by exposure to an organic amine-containing dopant. Illustrative exa... | 07/29/2008 |
| 7405128 | Dotted channel MOSFET and method A improved MOSFET (50, 51, 75, 215) has a source (60) and drain (62) in a semiconductor body (56), surmounted by an insulated control gate (66) located over the body (56) between the source (60) and drain (62) ... | 07/29/2008 |
| 7393737 | Semiconductor device and a method of manufacturing the same A semiconductor device which, in spite of the existence of a dummy active region, eliminates the need for a larger chip area and improves the surface flatness of the semiconductor substrate. In the process of manufacturing it, a thick gate insulating film for a high... | 07/01/2008 |
| 7371667 | Semiconductor device and method of fabricating same There are disclosed TFTs that have excellent characteristics and can be fabricated with a high yield. The TFTs are fabricated, using an active layer crystallized by making use of nickel. Gate electrodes are comprising tantalum. Phosphorus is introduced into source/d... | 05/13/2008 |
| 7368357 | Semiconductor device having a graded LDD region and fabricating method thereof A semiconductor device and fabricating method thereof in which a lightly doped drain junction is graded using a diffusion property of dopant implanted in heavily doped source/drain region are disclosed. An example semiconductor device includes a gate electrode havin... | 05/06/2008 |
| 7364951 | Nonvolatile semiconductor memory device and method for manufacturing the same A method for manufacturing a nonvolatile semiconductor memory device having a step of forming a first gate electrode on a peripheral circuit portion and a second gate electrode on a memory cell portion, a step of introducing impurity into the peripheral circuit port... | 04/29/2008 |
| 7344947 | Methods of performance improvement of HVMOS devices Methods fabricate DEMOS devices having varied channel lengths and substantially similar threshold voltages. A threshold voltage is selected for first and second devices. First and second well regions are formed. First and second drain extension regions are formed wi... | 03/18/2008 |
| 7342276 | Method and apparatus utilizing monocrystalline insulator A semiconductor device, including: a semiconductor material; a conductive element; and a substantially monocrystalline insulator disposed between the semiconductor material and the conductive eleme... | 03/11/2008 |
| 7332775 | Protruding spacers for self-aligned contacts A protruding spacer that protrudes above the top surface of a gate electrode structure provides enhanced resistance to exposure of the gate electrode during the etch process used to form self-aligned contacts. The protruding spacer may be formed using an amorphous c... | 02/19/2008 |
| 7316968 | Methods of forming semiconductor devices having multiple channel MOS transistors In a method of manufacturing a semiconductor device, a preliminary active pattern including gate layers and channel layers is formed on a substrate. The gate layers and the channel layers are alternatively stacked. A hard mask is formed on the preliminary active pat... | 01/08/2008 |
| 7314801 | Semiconductor device having a surface conducting channel and method of forming A semiconductor device including a metal oxide layer, a channel area of the metal oxide layer, a preservation layer formed on the channel area of the metal oxide layer, and at least two channel contacts coupled to the channel area of the metal oxide layer, and a met... | 01/01/2008 |
| 7306998 | Formation of abrupt junctions in devices by using silicide growth dopant snowplow effect A method of forming an abrupt junction device with a semiconductor substrate is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed on the gate dielectric. A sidewall spacer is formed on the semiconductor substrate adjacent the g... | 12/11/2007 |
| 7285477 | Dual wired integrated circuit chips A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with fir... | 10/23/2007 |
| 7268387 | Semiconductor device and an electronic device The present invention provides a semiconductor nonvolatile memory in which writing or erasing of storing information can be carried out at a high speed with low consumption power and in which dispersion width of a threshold voltage after writing or erasing is very n... | 09/11/2007 |
| 7253066 | MOSFET with decoupled halo before extension An inverse-T transistor is formed by a method that decouples the halo implant, the deep S/D implant and the extension implant, so that the threshold voltage can be set by adjusting the halo implant without being affected by changes to the extension implant that are ... | 08/07/2007 |
| 7221021 | Method of forming high voltage devices with retrograde well A high voltage device with retrograde well is disclosed. The device comprises a substrate, a gate region formed on the substrate, and a retrograde well placed in the substrate next to the gate region, wherein the retrograde well reduces a dopant concentration on the... | 05/22/2007 |
| 7195967 | Nonvolatile semiconductor memory device and manufacturing method thereof In a channel region between the source/drain diffusion layers, impurities of the same conductivity type as the well are doped in an area apart from the diffusion regions. By using as a mask the gate formed in advance, tilted ion implantation in opposite directions i... | 03/27/2007 |
| 7189648 | Method for reducing the contact resistance of the connection regions of a semiconductor device One embodiment of the invention relates to a method for fabricating a semiconductor device having a semiconductor structure with a silicon region which forms at least one connection region in and/or on a surface of a substrate. The method comprises forming a metal c... | 03/13/2007 |
| 7183161 | Programming and erasing structure for a floating gate memory cell and method of making A floating gate memory cell has a floating gate in which there are two floating gate layers. The top layer is etched to provide a contour in the top layer while leaving the lower layer unchanged. The control gate follows the contour of the floating gate to increase ... | 02/27/2007 |
| 7179712 | Multibit ROM cell and method therefor To increase the density of memory cells, a multibit memory cell (10, 50, 80, 110) can be manufactured by preventing the formation of at least one of the extension regions usually formed for the source or drain region. In one embodiment, a single mask (24 | 02/20/2007 |
| 7176109 | Method for forming raised structures by controlled selective epitaxial growth of facet using spacer Raised structures comprising overlying silicon layers formed by controlled selective epitaxial growth, and methods for forming such raised-structure on a semiconductor substrate are provided. The structures are formed by selectively growing an initial epitaxial laye... | 02/13/2007 |
| 7172933 | Recessed polysilicon gate structure for a strained silicon MOSFET device A method of forming a channel region for a MOSFET device in a strained silicon layer via employment of adjacent and surrounding silicon-germanium shapes, has been developed. The method features simultaneous formation of recesses in a top portion of a conductive gate... | 02/06/2007 |
| 7166525 | High temperature hydrogen annealing of a gate insulator layer to increase etching selectivity between conductive gate structure and gate insulator layer A method of defining a conductive gate structure for a MOSFET device wherein the etch rate selectivity of the conductive gate material to an underlying insulator layer is optimized, has been developed. After formation of a nitrided silicon dioxide layer, to be used ... | 01/23/2007 |
| 7151033 | Method for manufacturing a semiconductor device having a low junction leakage current A method for manufacturing a DRAM device includes a hydrogenating step conducted to source/drain diffused regions in a hydrogen ambient at a substrate temperature not lower than 350 degrees C., and a dehydrogenating step in an inactive gas ambient at a substrate tem... | 12/19/2006 |
| 7145191 | P-channel field-effect transistor with reduced junction capacitance The source/drain zones (140 and 142 or 160 and 162) of a p-channel IGFET (120 or 122) are provided with graded-junction characteristics to reduce junction capacitance, thereby increasing switching speed. Each source/drain zo... | 12/05/2006 |
| 7084036 | Data writing method for mask read only memory A data writing method for mask read only memory using different doses of ion implantations to perform the data writing of Mask Read Only Memory. A semiconductor substrate having a plurality of gate structures is provided. The different ion implantations are performe... | 08/01/2006 |
| 7064026 | Semiconductor device having shared contact and fabrication method thereof Semiconductor devices and methods of fabrication. A device includes a semiconductor substrate, a gate electrode insulated from the semiconductor substrate by a gate insulation layer, LDD-type source/drain regions formed at both sides of the gate electrode, an interl... | 06/20/2006 |
