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| Number | Title | Issue Date |
| 8187943 | MOS device resistant to ionizing radiation An embodiment of a MOS device resistant to ionizing-radiation, has: a surface semiconductor layer with a first type of conductivity; a gate structure formed above the surface semiconductor layer, and constituted by a dielectric gate region and a gate-electrode regio... | 05/29/2012 |
| 8143130 | Method of manufacturing depletion MOS device The present invention discloses a method of manufacturing a depletion metal oxide semiconductor (MOS) device. The method includes: providing a substrate; forming a first conductive type well and an isolation region in the substrate to define a device area; defining ... | 03/27/2012 |
| 8133790 | Semiconductor device and method for fabricating the same A semiconductor device and a method of manufacturing a semiconductor device. A method may include forming a first well by injecting first conduction type impurity ions on and/or over a semiconductor substrate, forming an extended drain region overlapped with a regio... | 03/13/2012 |
| 8129246 | Advanced CMOS using super steep retrograde wells The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS tran... | 03/06/2012 |
| 8067288 | Configuration and method of manufacturing the one-time programmable (OTP) memory cells This invention discloses a method for manufacturing a one-time programmable (OTP) memory includes a first and second MOS transistors connected in parallel and controlled by a common gate formed with a single polysilicon stripe. The method further comprises a step of... | 11/29/2011 |
| 8053321 | Formation of standard voltage threshold and low voltage threshold MOSFET devices Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within... | 11/08/2011 |
| 8053320 | Semiconductor device and manufacturing method thereof An aspect of the present invention provides a semiconductor device that includes a first conductivity type semiconductor body, a source region in contact with the semiconductor body, whose bandgap is different from that of the semiconductor body, and which formed he... | 11/08/2011 |
| 8048748 | Reducing contamination in a process flow of forming a channel semiconductor alloy in a semiconductor device In sophisticated approaches for forming high-k metal gate electrode structures in an early manufacturing stage, a threshold adjusting semiconductor alloy may be deposited on the basis of a selective epitaxial growth process without affecting the back side of the sub... | 11/01/2011 |
| 8030166 | Lateral pocket implant charge trapping devices A charge trapping memory cell is described, having pocket implants along the sides of the channel and having the same conductivity type as the channel, and which implants have a concentration of dopants higher than in the central region of the channel. This effectiv... | 10/04/2011 |
| 7981749 | MOS structures that exhibit lower contact resistance and methods for fabricating the same MOS structures that exhibit lower contact resistance and methods for fabricating such MOS structures are provided. In one method, a semiconductor substrate is provided and a gate stack is fabricated on the semiconductor substrate. An impurity-doped region within the... | 07/19/2011 |
| 7968412 | Manufacturing process of a vertical-conduction MISFET device with gate dielectric structure having differentiated thickness and vertical-conduction MISFET device thus manufacture According to an embodiment of a method for manufacturing a MISFET device, in a semiconductor wafer, a semiconductor layer is formed, having a first type of conductivity and a first level of doping. A first body region and a second body region, having a second type o... | 06/28/2011 |
| 7968411 | Threshold voltage adjustment for long-channel transistors A threshold voltage adjusted long-channel transistor fabricated according to short-channel transistor processes is described. The threshold-adjusted transistor includes a substrate with spaced-apart source and drain regions formed in the substrate and a channel regi... | 06/28/2011 |
| 7943468 | Penetrating implant for forming a semiconductor device A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adj... | 05/17/2011 |
| 7883977 | Advanced CMOS using super steep retrograde wells The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS tran... | 02/08/2011 |
| 7883976 | Structure and method for manufacturing device with planar halo profile A semiconductor device and method for manufacturing the device with a planar halo profile is provided. The semiconductor device can be a MOSFET. The method of forming the structure includes forming an angled spacer adjacent a gate structure and implanting a halo imp... | 02/08/2011 |
| 7879678 | Methods of enhancing performance of field-effect transistors and field-effect transistors made thereby Methods of enhancing the performance of a field-effect transistor (FET) by providing a percolating network of metallic islands to the inversion layer of the FET so as to effectively reduce the channel length of the FET. The metal islands can be provided in a number ... | 02/01/2011 |
| 7867861 | Semiconductor device employing precipitates for increased channel stress A method for fabricating a semiconductor device including implanting a selected material at a desired target depth below a surface of a silicon substrate, performing an annealing process to create a band of precipitates formed from the selected material and the sili... | 01/11/2011 |
| 7795098 | Rotated field effect transistors and method of manufacture An apparatus and method for manufacturing rotated field effect transistors. The method comprises providing a substrate including a first gate structure and a second gate structure, which are not parallel to each other. The method further includes performing a first ... | 09/14/2010 |
| 7732286 | Buried biasing wells in FETs (Field Effect Transistors) A method for fabricating a semiconductor structure. The semiconductor structure comprises first and second source/drain regions; a channel region disposed between the first and second source/drain regions; a buried well region in physical contact with the channel re... | 06/08/2010 |
| 7696049 | Method to manufacture LDMOS transistors with improved threshold voltage control A double diffused region (65), (75), (85) is formed in a semiconductor substrate or in an epitaxial layer (20) formed on the semiconductor substrate. The double diffused region is formed by first implanting light implant specie such as bo... | 04/13/2010 |
| 7682913 | Process for making a MCSFET A process for making a MCSFET includes providing a first implant through a first side of an elongated stack, and then providing a second implant through a second side of the stack. The first implant has a dose different than the dose of the second implant, so that f... | 03/23/2010 |
| 7655523 | Advanced CMOS using super steep retrograde wells The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS tran... | 02/02/2010 |
| 7648883 | Phosphorous doping methods of manufacturing field effect transistors having multiple stacked channels Integrated circuit field effect transistors are manufactured by forming a pre-active pattern on a surface of a substrate, while refraining from doping the pre-active pattern with phosphorus. The pre-active pattern includes a series of interchannel layers and channel... | 01/19/2010 |
| 7645673 | Method for generating a deep N-well pattern for an integrated circuit design A method for the design and layout for a patterned deep N-well. A Tile is specified as a fundamental building block for the deep N-well pattern. The tile comprises a first element on a first layer and may comprise a second element on a second layer. A two dimensiona... | 01/12/2010 |
| 7605041 | Semiconductor device and its manufacture method Multiple kinds of transistors exhibiting desired characteristics are manufactured in fewer processes. A semiconductor device includes an isolation region reaching a first depth, first and second wells of first conductivity type, a first transistor formed in the firs... | 10/20/2009 |
| 7601598 | Reverse metal process for creating a metal silicide transistor gate structure The present invention teaches a method of forming a MOSFET transistor having a silicide gate which is not subject to problems produced by etching a metal containing layer when forming the gate stack structure. A gate stack is formed over a semiconductor substrate co... | 10/13/2009 |
| 7598146 | Self-aligned gate and method A semiconductor structure comprises a silicon substrate of a first conductivity type including wells of a second conductivity type formed on a surface thereof. The wells may be laterally isolated by shallow trench isolation. Transistors are formed in the wells by fi... | 10/06/2009 |
| 7563682 | LDMOS transistor device, integrated circuit, and fabrication method thereof An LDMOS transistor device in an integrated circuit comprises a semiconductor substrate (10), a gate region (1) including a gate semiconductor layer region (2; 2′; 151) on top of a gate insulation layer region (3; 141), source (4... | 07/21/2009 |
| 7550354 | Nanoelectromechanical transistors and methods of forming same Nanoelectromechanical transistors (NEMTs) and methods of forming the same are disclosed. In one embodiment, an NEMT may include a substrate including a gate, a source region and a drain region; an electromechanically deflectable nanotube member; and a channel member... | 06/23/2009 |
| 7524728 | Thin film transistor manufacturing method and organic electroluminescent display device The invention reduces display unevenness of a horizontal streak and a vertical streak of an organic EL display device to improve display quality. A silicon oxide film is deposited on a glass substrate by a plasma CVD method, and an amorphous silicon film is further ... | 04/28/2009 |
| 7501324 | Advanced CMOS using super steep retrograde wells The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS tran... | 03/10/2009 |
| 7488657 | Method and system for forming straight word lines in a flash memory array Embodiments of the present invention disclose a memory device having an array of flash memory cells with source contacts that facilitate straight word lines, and a method for producing the same. The array is comprised of a plurality of non-intersecting shallow trenc... | 02/10/2009 |
| 7470593 | Method for manufacturing a cell transistor of a semiconductor memory device Disclosed is a method for manufacturing a cell transistor of a semiconductor memory device. The method comprises the steps of: forming device isolation films and a well on a semiconductor substrate; forming a threshold voltage adjust region by ion-implanting a first... | 12/30/2008 |
| 7465633 | Methods of forming field effect transistors and capacitor-free dynamic random access memory cells Methods of forming capacitor-free DRAM cells include forming a field effect transistor by forming a first semiconductor wafer having a channel region protrusion extending therefrom and surrounding the channel region protrusion by an electrical isolation region. A po... | 12/16/2008 |
| 7462543 | Flash memory cell transistor with threshold adjust implant and source-drain implant formed using a single mask A method for forming an NMOS transistor for use in a flash memory cell on a P-type semiconductor structure includes forming a photoresist layer over the semiconductor structure and patterning the photoresist layer using a source/drain mask for the NMOS transistor; f... | 12/09/2008 |
| 7442971 | Self-biasing transistor structure and an SRAM cell having less than six transistors By providing a self-biasing semiconductor switch, an SRAM cell having a reduced number of individual active components may be realized. In particular embodiments, the self-biasing semiconductor device may be provided in the form of a double channel field effect tran... | 10/28/2008 |
| 7439140 | Formation of standard voltage threshold and low voltage threshold MOSFET devices Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within... | 10/21/2008 |
| 7439165 | Method of fabricating tensile strained layers and compressive strain layers for a CMOS device A process for forming both tensile and compressive strained silicon layers to accommodate channel regions of MOSFET or CMOS devices has been developed. After formation of shallow trench isolation structures as well as application of high temperature oxidation and ac... | 10/21/2008 |
| 7432136 | Transistors with controllable threshold voltages, and various methods of making and operating same In one illustrative embodiment, the method comprises providing an SOI substrate comprised of an active layer, a buried insulation layer and a bulk substrate, the active layer being doped with a first type of dopant material, the bulk substrate having an inner well f... | 10/07/2008 |
| 7432164 | Semiconductor device comprising a transistor having a counter-doped channel region and method for forming the same A method for making a semiconductor device includes providing a first substrate region and a second substrate region, wherein at least a part of the first substrate region has a first conductivity type and at least a part of the second substrate region has a second ... | 10/07/2008 |
