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| Number | Title | Issue Date |
| 8143129 | Integration of non-volatile charge trap memory devices and logic CMOS devices A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be f... | 03/27/2012 |
| 8093128 | Integration of non-volatile charge trap memory devices and logic CMOS devices A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be f... | 01/10/2012 |
| 8093129 | Methods of forming memory cells Some embodiments include methods of forming memory cells. A semiconductor construction may be provided, with such construction including tunnel dielectric material over a semiconductor substrate. The construction may be placed within a chamber. While the constructio... | 01/10/2012 |
| 8058131 | Semiconductor integrated circuit device and method of producing the same A semiconductor integrated circuit device includes a substrate, a nonvolatile memory device formed in a memory cell region of the substrate, and a semiconductor device formed in a device region of the substrate. The nonvolatile memory device has a multilayer gate el... | 11/15/2011 |
| 8048747 | Method of manufacturing embedded metal-oxide-nitride-oxide-silicon memory device The present disclosure fabricates an embedded metal-oxide-nitride-oxide-silicon (MONOS) memory device. The memory device is stacked with memory layers having a low aspect ratio. The memory device can be easily fabricated with only two extra masks for saving cost. Th... | 11/01/2011 |
| 8034690 | Method of etching oxide layer and nitride layer An exemplary method of etching an oxide layer and a nitride layer is provided. In particular, a substrate is provided. A surface of the substrate has an isolating structure projecting therefrom. A first oxide layer, a nitride layer and a second oxide layer are seque... | 10/11/2011 |
| 8030165 | Poly gate etch method and device for sonos-based flash memory A method for forming flash memory devices is provided. The method includes providing a semiconductor substrate, which comprises a silicon material and has a periphery region and a cell region. The method further includes forming an isolation structure between the ce... | 10/04/2011 |
| 8017485 | Methods of fabricating a semiconductor device Methods of fabricating a semiconductor device are provided, the methods include forming a first dielectric layer, a data storage layer, and a second dielectric layer, which are sequentially stacked, on a semiconductor substrate. A mask having a first opening exposin... | 09/13/2011 |
| 8003468 | Separation methods for semiconductor charge accumulation layers and structures thereof Devices and methods for isolating adjacent charge accumulation layers in a semiconductor device are disclosed. In one embodiment, a semiconductor device comprises a bit line formed in a semiconductor substrate, a charge accumulation layer formed on the semiconductor... | 08/23/2011 |
| 8003469 | Method of manufacturing non-volatile semiconductor devices A non-volatile semiconductor device includes a memory cell in a first area of a substrate, a low voltage transistor in a second area of the substrate, and a high voltage transistor in a third area of the substrate. The memory cell includes a tunnel insulation layer ... | 08/23/2011 |
| 7994012 | Semiconductor device and a method of manufacturing the same To improve characteristics of a semiconductor device having a nonvolatile memory. There is provided a semiconductor device having a nonvolatile memory cell that performs memory operations by transferring a charge to/from a charge storage film, wherein the nonvolatil... | 08/09/2011 |
| 7955935 | Non-volatile memory cell devices and methods A method of fabricating a memory cell including forming nanodots over a first dielectric layer and forming an intergate dielectric layer over the nanodots, where the intergate dielectric layer encases the nanodots. To form sidewalls of the memory cell, a portion of ... | 06/07/2011 |
| 7947558 | Electromechanical memory devices and methods of manufacturing the same In a memory device and a method of forming the same, in one embodiment, the memory device comprises a first word line structure on a substrate, the first word line structure extending in a first direction. A bit line is provided over the first word line structure an... | 05/24/2011 |
| 7897471 | Method and apparatus to improve the reliability of the breakdown voltage in high voltage devices A structure to diminish high voltage instability in a high voltage device when under stress includes an amorphous silicon layer over a field oxide on the high voltage device. ... | 03/01/2011 |
| 7883975 | Method for fabricating a non-volatile memory including converting a silicon layer-which formed over a stacked structure having a charge storage layer-into an insulating layer A method for fabricating a non-volatile memory is provided. The method includes a stacked structure and a consuming layer are formed in sequence over a substrate. A converting process is performed at a peripheral region of the consuming layer to form a first insulat... | 02/08/2011 |
| 7820515 | Nonvolatile semiconductor memory element excellent in charge retention properties and process for producing the same A process for producing a nonvolatile semiconductor memory having a mixed or laminated structure of a hardly oxidizable material composed of a hardly oxidizable element having Gibbs' free energy for forming oxide higher than that of Si under the same temperature con... | 10/26/2010 |
| 7820514 | Methods of forming flash memory devices including blocking oxide films A method of forming a flash memory device can include forming a tunneling oxide film on a semiconductor substrate, forming a charge storing layer on the tunneling oxide film, forming a first blocking oxide film on the charge storing layer at a first temperature, for... | 10/26/2010 |
| 7732285 | Semiconductor device having self-aligned epitaxial source and drain extensions A method of forming a transistor with self-aligned source and drain extensions in close proximity to a gate dielectric layer of the transistor comprises forming a gate stack on a substrate, implanting a dopant into regions of the substrate adjacent to the gate stack... | 06/08/2010 |
| 7727843 | Semiconductor element, semiconductor storage device using the same, data writing method thereof, data reading method thereof, and manufacturing method of those The invention relates to a semiconductor element used for a nonvolatile semiconductor storage device or the like, a semiconductor storage device using the same, a data writing method thereof, a data reading method thereof and a manufacturing method of those, and has... | 06/01/2010 |
| 7687360 | Method of forming spaced-apart charge trapping stacks Methods are provided for fabricating memory devices. A method comprises fabricating charge-trapping stacks overlying a silicon substrate and forming bit line regions in the substrate between the charge trapping stacks. Insulating elements are formed overlying the bi... | 03/30/2010 |
| 7635633 | Non-volatile memory device and method of manufacturing the same In a non-volatile memory device and a method of manufacturing the non-volatile memory device, a tunnel insulating layer, a charge trapping layer, a dielectric layer and a conductive layer may be sequentially formed on a channel region of a substrate. The conductive ... | 12/22/2009 |
| 7622355 | Write once read only memory employing charge trapping in insulators Structures and methods for write once read only memory employing charge trapping in insulators are provided. The write once read only memory cell includes a metal oxide semiconductor field effect transistor having a first source/drain region, a second source/drain r... | 11/24/2009 |
| 7608514 | MSM binary switch memory A metal/semiconductor/metal (MSM) binary switch memory device and fabrication process are provided. The device includes a memory resistor bottom electrode, a memory resistor material over the memory resistor bottom electrode, and a memory resistor top electrode over... | 10/27/2009 |
| 7575978 | Method for making conductive nanoparticle charge storage element Isolated conductive nanoparticles on a dielectric layer and methods of fabricating such isolated conductive nanoparticles provide charge storage units in electronic structures for use in a wide range of electronic devices and systems. The isolated conductive nanopar... | 08/18/2009 |
| 7557009 | Process for controlling performance characteristics of a negative differential resistance (NDR) device A variety of processes are disclosed for controlling NDR characteristics for an NDR element, such as peak-to-valley ratio (PVR), NDR onset voltage (VNDR) and related parameters. The processes are based on conventional semiconductor manufacturing operation... | 07/07/2009 |
| 7557008 | Method of making a non-volatile memory device A method forms a nonvolatile memory device using a semiconductor substrate. A charge storage layer is formed overlying the semiconductor substrate and a layer of gate material is formed overlying the charge storage layer to form a control gate electrode. A protectiv... | 07/07/2009 |
| 7550353 | Method of forming semiconductor device One embodiment of a method for forming a semiconductor device can include forming a gate pattern on a semiconductor substrate and performing a selective re-oxidation process on the gate pattern in gas ambient including hydrogen, oxygen, and nitrogen. When the gate p... | 06/23/2009 |
| 7534688 | Nonvolatile memory device with a non-planar gate-insulating layer and method of fabricating the same A non-volatile memory device with a non-planar gate insulating layer and a method of fabricating the same are provided. The device includes a tunnel insulating pattern, a charge storage layer, an upper insulating layer and a control gate electrode which are sequenti... | 05/19/2009 |
| 7442987 | Non-volatile memory devices including divided charge storage structures A semiconductor memory device includes a substrate having first and second source/drain regions therein and a channel region therebetween. The device also includes first and second charge storage layers on the channel region, a first insulating layer on the channel ... | 10/28/2008 |
| 7439134 | Method for process integration of non-volatile memory cell transistors with transistors of another type A method for making a semiconductor device having non-volatile memory cell transistors and transistors of another type is provided. In the method, a substrate is provided having an NVM region, a high voltage (HV) region, and a low voltage (LV) region. The method inc... | 10/21/2008 |
| 7432158 | Method for retaining nanocluster size and electrical characteristics during processing A method of making a semiconductor device includes a substrate having a semiconductor layer having a first portion for non-volatile memory and a second portion exclusive of the first portion. A first dielectric layer is formed over the semiconductor layer. A first p... | 10/07/2008 |
| 7419868 | Gated diode nonvolatile memory process A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Various embodiments may include or exclude a diffusion barrier structure between the diode nodes. Example embodiments include the indiv... | 09/02/2008 |
| 7416940 | Methods for fabricating flash memory devices Methods for fabricating a flash memory device are provided. A method comprises forming a plurality of gate stacks overlying a substrate. Each gate stack comprises a charge trapping layer and a control gate. The control gate is a first distance from the substrate. Ad... | 08/26/2008 |
| 7416933 | Methods of enabling polysilicon gate electrodes for high-k gate dielectrics Complementary transistors and methods of forming the complementary transistors on a semiconductor assembly are described. The transistors are formed with an optional interfacial oxide, such as SiO2 or oxy-nitride, to overlay a semiconductor substrate whic... | 08/26/2008 |
| 7381620 | Oxygen elimination for device processing A method includes forming at least a portion of a semiconductor device in a processing chamber containing oxygen and removing substantially all of the oxygen from the processing chamber. The method further includes forming remaining portions of the semiconductor dev... | 06/03/2008 |
| 7371649 | Method of forming carbon-containing silicon nitride layer A method for forming a carbon-containing silicon nitride layer with superior uniformity by low pressure chemical vapor deposition (LPCVD) using disilane, ammonia and at least one carbon-source precursor as reactant gases is provided. ... | 05/13/2008 |
| 7368356 | Transistor with doped gate dielectric A transistor and method of manufacture thereof. A semiconductor workpiece is doped before depositing a gate dielectric material. Using a separate anneal process or during subsequent anneal processes used to manufacture the transistor, dopant species from the doped r... | 05/06/2008 |
| 7361543 | Method of forming a nanocluster charge storage device An integrated circuit and method of forming an integrated circuit having a memory portion minimizes an amount of oxidation of nanocluster storage elements in the memory portion. A first region of the integrated circuit has non-memory devices, each having a control e... | 04/22/2008 |
| 7358126 | Dual damascene structure and methods of forming the same A dual damascene structure and a method of forming a dual damascene structure are disclosed. The dual damascene structure includes an insulation member, a single crystal member and a filling member. The insulation member has an opening having a dual damascene shape.... | 04/15/2008 |
| 7355238 | Nonvolatile semiconductor memory device having nanoparticles for charge retention A nonvolatile semiconductor memory device including a source region and a drain region formed on a surface of a semiconductor substrate, a channel-forming region formed so as to connect the source region and the drain region or so as to be sandwiched between the sou... | 04/08/2008 |
