Did You Know...
...that the inventor of the electric motor was a blacksmith named Thomas Davenport? Described as "a brilliantly unsuccessful inventor", Davenport invented the first rotary electric motor. In 1836 he headed out -- on foot -- from his Vermont home to file a patent application at the Patent Office in Washington, D.C. By the time he got there, he had squandered away his money and couldn't afford the $30 filing fee so he turned around and went home. When he later mailed in his application with money he'd raised, the Patent office was destroyed in a fire. He did finally get credit for his invention on Feb. 5, 1837.
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| Number | Title | Issue Date |
| 8178412 | Semiconductor memory device and method of manufacturing the same A plurality of memory cells each constituted of a memory cell transistor having a gate electrode in a laminated structure composed of a charge storage layer and a control gate layer and a select transistor having source/drain diffusion layers while one of the source... | 05/15/2012 |
| 8178413 | Low-temperature grown high quality ultra-thin CoTiOgate dielectrics A gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO2 gate oxides are provided. Gate oxides formed from alloys such as cobalt-titanium are thermodynamically stable s... | 05/15/2012 |
| 8168502 | Tantalum silicon oxynitride high-K dielectrics and metal gates Electronic apparatus and methods of forming the electronic apparatus include a tantalum silicon oxynitride film on a substrate for use in a variety of electronic systems. The tantalum silicon oxynitride film may be structured as one or more monolayers. The tantalum ... | 05/01/2012 |
| 8163620 | Method for etching Mo-based metal gate stack with aluminium nitride barrier The present application discloses a method for etching a Mo-based metal gate stack with an aluminum nitride barrier, comprising the steps of forming a SiO2 interface layer, a high K dielectric layer, a Mo-based metal gate layer, an AlN barrier layer, a si... | 04/24/2012 |
| 8153491 | Non-volatile memory semiconductor device having an oxide-nitride-oxide (ONO) top dielectric layer A non-volatile memory (NVM) cell includes a silicon substrate having a main surface, a source region in a portion of the silicon substrate, a drain region in a portion of the silicon substrate, and a well region disposed in a portion of the silicon substrate between... | 04/10/2012 |
| 8153492 | Self-aligned V-channel MOSFET Forming a high-κ/metal gate field effect transistor using a gate last process in which the channel region has a curved profile thus increasing the effective channel length improves the short channel effect. During the high-κ/metal gate process, after the sacrifici... | 04/10/2012 |
| 8143128 | Multilayer dielectric defect method A method forms a first inorganic dielectric layer having a first concentration of defects and a second inorganic dielectric layer in contact with a first layer and having a second lesser concentration of defects. ... | 03/27/2012 |
| 8124485 | Molecular spacer layer for semiconductor oxide surface and high-K dielectric stack A process for defining a functional area in a semiconductor device comprising a semiconductor substrate contiguous with a gate dielectric layer whose dielectric constant is higher than silicon oxide and an oxide capping layer positioned on the gate dielectric layer ... | 02/28/2012 |
| 8124484 | Forming a MOS memory device having a dielectric film laminate as a charge accumulation region To manufacture a MOS memory device having a dielectric film laminate in which adjacent dielectric films have band-gaps of different magnitudes, a plasma processing device which transmits microwaves to a chamber by means of a planar antenna having a plurality of hole... | 02/28/2012 |
| 8119488 | Scalable quantum well device and method for manufacturing the same A quantum well device and a method for manufacturing the same are disclosed. In one aspect, the device includes a quantum well region overlying a substrate, a gate region overlying a portion of the quantum well region, a source and drain region adjacent to the gate ... | 02/21/2012 |
| 8110469 | Graded dielectric layers Graded dielectric layers and methods of fabricating such dielectric layers provide dielectrics in a variety of electronic structures for use in a wide range of electronic devices and systems. In an embodiment, a dielectric layer is graded with respect to a doping pr... | 02/07/2012 |
| 8105909 | Method of fabricating non-volatile memory device A method of fabricating a non-volatile memory device includes: forming a tunnel insulation layer pattern and a floating gate electrode layer pattern over a semiconductor substrate; forming an isolation trench by etching an exposed portion of the semiconductor substr... | 01/31/2012 |
| 8076207 | Gate structure and method of making the same A method of making a gate structure includes the following steps. First, a gate is formed. Then, a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer are formed to cover the gate from bottom to top. Later, a dry etching is performed... | 12/13/2011 |
| 8076206 | Method for manufacturing SONOS flash memory A method for manufacturing a semiconductor device which includes steps of forming a dummy layer on a semiconductor substrate, forming a groove 12 in the semiconductor substrate while using the dummy layer as a mask, forming a tunnel insulating film and a trap layer ... | 12/13/2011 |
| 8071453 | Method of ONO integration into MOS flow A method of ONO integration of a non-volatile memory device (e.g. EEPROM, floating gate FLASH and SONOS) into a baseline MOS device (e.g. MOSFET) is described. In an embodiment the bottom two ONO layers are formed prior to forming the channel implants into the MOS d... | 12/06/2011 |
| 8071452 | Atomic layer deposition of hafnium lanthanum oxides There is provided an improved method for depositing thin films using precursors to deposit binary oxides by atomic layer deposition (ALD) techniques. Also disclosed is an ALD method for depositing a high-k dielectric such as hafnium lanthanum oxide (HfLaO) on a subs... | 12/06/2011 |
| 8058130 | Method of forming a nitrogen-enriched region within silicon-oxide-containing masses The invention encompasses a method of incorporating nitrogen into a silicon-oxide-containing layer. The silicon-oxide-containing layer is exposed to a nitrogen-containing plasma to introduce nitrogen into the layer. The nitrogen is subsequently thermally annealed wi... | 11/15/2011 |
| 8048746 | Method of making flash memory cells and peripheral circuits having STI, and flash memory devices and computer systems having the same An integrated circuit includes flash memory cells, and peripheral circuitry including low voltage transistors (LVT) and high voltage transistors (HVT). The integrated circuit includes a tunnel barrier layer comprising SiON, SiN or other high-k material. The tunnel b... | 11/01/2011 |
| 8026143 | Semiconductor element and manufacturing method thereof The object of the present invention is to provide a method of manufacturing high permittivity gate dielectrics for a device such as an MOSFET. A HfSiO film is formed by sputtering a Hf metal film on a SiO2 film (or a SiON film) on a Si wafer. A TiO2 ... | 09/27/2011 |
| 8021948 | Scalable interpoly dielectric stacks with improved immunity to program saturation A method for manufacturing a non-volatile memory device is described. The method comprises growing a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored. A non-volatile memory device is also described... | 09/20/2011 |
| 8017484 | Transistor device and methods of manufacture thereof Methods of forming transistor devices and structures thereof are disclosed. A first dielectric material is formed over a workpiece, and a second dielectric material is formed over the first dielectric material. The workpiece is annealed, causing a portion of the sec... | 09/13/2011 |
| 8008156 | Nitride read only memory device with buried diffusion spacers and method for making the same A method for making a nitride read only memory device with buried diffusion spacers is disclosed. An oxide-nitride-oxide (ONO) layer is formed on top of a silicon substrate, and a polysilicon gate is formed over the ONO layer. The polysilicon gate is formed less tha... | 08/30/2011 |
| 8008155 | Gate electrode structure An electrode structure, e.g., a gate electrode for a transistor, includes: a volume of semiconductor material; a gate oxide on the semiconductor volume; a barrier layer, including silicon nitride, on the gate oxide layer; an adhesion layer on the barrier layer; and ... | 08/30/2011 |
| 7998820 | High-k gate dielectric and method of manufacture A device and method of formation are provided for a high-k gate dielectric and gate electrode. The high-k dielectric material is formed, and a silicon-rich film is formed over the high-k dielectric material. The silicon-rich film is then treated through either oxida... | 08/16/2011 |
| 7994011 | Method of manufacturing nonvolatile memory device and nonvolatile memory device manufactured by the method A method of manufacturing a nonvolatile memory device having a three-dimensional memory device includes alternately stacking a plurality of first and second material layers having a different etching selectivity on a semiconductor substrate; forming an opening penet... | 08/09/2011 |
| 7968410 | Method of fabricating a semiconductor device using a full silicidation process A method of fabricating a semiconductor device includes: forming a first polysilicon layer having a first thickness in a peripheral circuit region formed on a substrate; forming a stack structure comprising a first tunneling insulating layer, a charge trap layer, an... | 06/28/2011 |
| 7960235 | Method for manufacturing a MOSFET with a surrounding gate of bulk Si A method for manufacturing a bulk Si nanometer surrounding-gate MOSFET based on a quasi-planar process, including: local oxidation isolation or shallow trench isolation; depositing buffer SiO2 oxide layer/SiN dielectric layer on the bulk Si; electron beam... | 06/14/2011 |
| 7955934 | Nitride read only memory device with buried diffusion spacers and method for making the same A method for making a nitride read only memory device with buried diffusion spacers is disclosed. An oxide-nitride-oxide (ONO) layer is formed on top of a silicon substrate, and a polysilicon gate is formed over the ONO layer. The polysilicon gate is formed less tha... | 06/07/2011 |
| 7955933 | Method of manufacturing nonvolatile semiconductor memory device A method of manufacturing a nonvolatile semiconductor memory device includes the steps of preparing a wafer having multiple memory cells, each memory cell having a gate electrode formed on a semiconductor substrate, charge storage units formed on both sides of the g... | 06/07/2011 |
| 7932154 | Method of fabricating non-volatile flash memory device having at least two different channel concentrations In a non-volatile flash memory device, and a method of fabricating the same, the device includes a semiconductor substrate, a source region and a drain region disposed in the semiconductor substrate to be spaced apart from each other, a tunneling layer pattern, a ch... | 04/26/2011 |
| 7927953 | Nonvolatile semiconductor memory device and method for manufacturing the same On a silicon substrate is formed a stacked body by alternately stacking a plurality of silicon oxide films and silicon films, a trench is formed in the stacked body, an alumina film, a silicon nitride film and a silicon oxide film are formed in this order on an inne... | 04/19/2011 |
| 7923336 | High-k dielectric film, method of forming the same and related semiconductor device A high-k dielectric film, a method of forming the high-k dielectric film, and a method of forming a related semiconductor device are provided. The high-k dielectric film includes a bottom layer of metal-silicon-oxynitride having a first nitrogen content and a first ... | 04/12/2011 |
| 7923335 | Non-volatile memory device and manufacturing method thereof A non-volatile memory device having a Polysilicon Oxide Nitride Oxide Semiconductor (SONOS) structure in which a charge trap layer is separated physically in a horizontal direction, and a method of manufacturing the same. The charge trap layer that traps electric ch... | 04/12/2011 |
| 7915126 | Methods of forming non-volatile memory cells, and methods of forming NAND cell unit string gates Some embodiments include methods of utilizing polysilazane in forming non-volatile memory cells. The memory cells may be multi-level cells (MLCs). The polysilazane may be converted to silicon nitride, silicon dioxide, or silicon oxynitride with thermal processing an... | 03/29/2011 |
| 7915127 | Manufacturing method of semiconductor device A method of forming a semiconductor device is described. First, a substrate is provided. Thereafter, a gate structure including, from bottom to top, a high-k layer, a work function metal layer, a wetting layer, a polysilicon layer and a mask layer is formed on the s... | 03/29/2011 |
| 7910446 | Integrated scheme for forming inter-poly dielectrics for non-volatile memory devices Electronic devices and methods for forming electronic devices that allow for a reduction in device dimensions while also maintaining or reducing leakage current for non-volatile memory devices are provided. In one embodiment, a method of fabricating a non-volatile m... | 03/22/2011 |
| 7897470 | Non-volatile memory cell device and methods A method of fabricating a memory cell including forming nanodots over a first dielectric layer and forming a second dielectric layer over the nanodots, where the second dielectric layer encases the nanodots. In addition, an intergate dielectric layer is formed over ... | 03/01/2011 |
| 7888219 | Methods of forming charge-trap type non-volatile memory devices Methods of forming a non-volatile memory device may include forming a tunnel insulating layer on a semiconductor substrate and forming a charge-trap layer on the tunnel insulating layer. A trench may then be formed extending through the tunnel insulating layer and t... | 02/15/2011 |
| 7888218 | Using thick spacer for bitline implant then remove The present invention pertains to a system method of forming at least a portion of a dual bit memory core array upon a semiconductor substrate, the method comprising forming adjacent first memory cell process assemblies; comprising a charge trapping dielectric, a fi... | 02/15/2011 |
| 7888217 | Method for fabricating a gate dielectric of a field effect transistor A method for fabricating a gate dielectric of a field effect transistor is disclosed herein. In one embodiment, the method includes the steps of removing a native oxide layer, forming an oxide layer, forming a gate dielectric layer over the oxide layer, oxidizing th... | 02/15/2011 |
