Class 438/286 - Asymmetric

Subclass of Class 438 - Semiconductor device manufacturing: process
Definition: Process for making an insulated gate field effect transistor
No. of patents: 814
Last issue date: 04/24/2012

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Number	Title	Issue Date
8163619	Fabrication of semiconductor structure having asymmetric field-effect transistor with tailored pocket portion along source/drain zone An asymmetric insulated-gate field effect transistor (100U or 102U) is provided along an upper surface of a semiconductor body so as to have first and second source/drain zones (240 and 242 or 280 and 282) laterally separate...	04/24/2012
8158482	Asymmetric transistor devices formed by asymmetric spacers and tilted implantation An asymmetric transistor configuration is disclosed in which asymmetric extension regions and/or halo regions may be combined with an asymmetric spacer structure which may be used to further adjust the overall dopant profile of the asymmetric transistor. ...	04/17/2012
8143127	Semiconductor device having asymmetric bulb-type recess gate and method for manufacturing the same A semiconductor device includes a silicon substrate; a device isolation structure formed in the silicon substrate to delimit an active region which has a pair of gate forming areas, a drain forming area between the gate forming areas, and source forming areas outsid...	03/27/2012
8138049	Fabrication of lateral double-diffused metal oxide semiconductor (LDMOS) devices Methods of making, structures, devices, and/or applications for lateral double-diffused metal oxide semiconductor (LDMOS) transistors are disclosed. In one embodiment, a method of fabricating an LDMOS transistor with source, drain, and gate regions on a substrate, c...	03/20/2012
8138050	Transistor device comprising an asymmetric embedded semiconductor alloy Transistor characteristics may be adjusted on the basis of asymmetrically formed cavities in the drain and source areas so as to maintain a strain-inducing mechanism while at the same time providing the possibility of obtaining asymmetric configuration of the drain ...	03/20/2012
8119487	Semiconductor device and method for fabricating the same A Semiconductor device and method for fabricating the same are disclosed. The method includes implanting first conduction type impurities into a semiconductor substrate to form a first well, implanting second conduction type impurities into the first well to form a ...	02/21/2012
8110468	DMOS-transistor having improved dielectric strength of drain and source voltages A DMOS-transistor having enhanced dielectric strength includes a first well region. A highly doped source region is located in the first well region and is complementarily doped thereto. A highly doped bulk connection region is located in the first well region and h...	02/07/2012
8076205	Semiconductor memory device and method of fabricating the same A semiconductor memory includes a memory cell array area provided with first and second memory cells and having a first active area and a first element isolation area constituting a line & space structure, and having a floating gate electrode and a control gate elec...	12/13/2011
8058129	Lateral double diffused MOS device and method for manufacturing the same A lateral double diffused metal oxide semiconductor (LDMOS) device and a method of manufacturing the same. A LDMOS device may include a high voltage well formed over a substrate, a reduced surface field region formed thereover which may be adjacent a body region, an...	11/15/2011
8053319	Method of forming a high voltage device A method of forming a device is presented. A substrate prepared with an active device region is provided. The active device region includes gate stack layers of a gate stack that includes at least a gate electrode layer over a gate dielectric layer. An implant mask ...	11/08/2011
8017483	Method of creating asymmetric field-effect-transistors The present invention provides a method of forming asymmetric field-effect-transistors. The method includes forming at least a first and a second gate-mask stack on top of a semiconductor substrate, wherein the first and second gate-mask stacks include at least, res...	09/13/2011
8012838	Method for fabricating lateral double diffused metal oxide semiconductor (LDMOS) transistor Disclosed is a method for fabricating a lateral double diffused metal oxide semiconductor (LDMOS) transistor, which includes implanting impurity ions onto a semiconductor substrate to form a drift region and a body region, forming a photoresist pattern to expose a r...	09/06/2011
7998819	Lateral drain MOSFET with improved clamping voltage control A lateral MOSFET having a substrate, first and second epitaxial layers grown on the substrate and a gate electrode formed on a gate dielectric which in turn is formed on a top surface of the second epitaxial layer. The second epitaxial layer comprises a drain region...	08/16/2011
7977197	Method for fabricating a transistor with reliable source doping A transistor and a method for the fabrication of transistors with different gate oxide thicknesses is proposed, in which for the doping of the source, the typical LDD implantation, which is formed after the fabrication of the gate electrode, is replaced by a doping ...	07/12/2011
7947557	Heterojunction tunneling field effect transistors, and methods for fabricating the same The present invention relates to a heterojunction tunneling effect transistor (TFET), which comprises spaced apart source and drain regions with a channel region located therebetween and a gate stack located over the channel region. The drain region comprises a firs...	05/24/2011
7897469	Impact ionization MOSFET method A method of manufacturing an I-MOS device includes forming a semiconductor layer (2) on a buried insulating layer (4). A gate structure (23) including a gate stack (14) is formed on the semiconductor layer, and used to (5) self ali...	03/01/2011
7892928	Method of forming asymmetric spacers and methods of fabricating semiconductor device using asymmetric spacers A method of fabricating asymmetrical spacers, structures fabricated using asymmetrical spacers and an apparatus for fabricating asymmetrical spacers. The method includes: forming on a substrate, a structure having a top surface and opposite first and second sidewall...	02/22/2011
7888216	Method of fabricating a high performance power MOS A method of fabricating a semiconductor device includes forming in the substrate a well region comprising a first type of dopant; forming in the well region a base region comprising a second type of dopant different from the first type of dopant; and forming in the ...	02/15/2011
7888215	CMOS image sensor with high full-well-capacity An image sensor with a high full-well capacity includes a photosensitive region, a transfer gate, and sidewall spacers. The photosensitive region is formed to accumulate an image charge in response to light. The transfer gate disposed adjacent to the photosensitive ...	02/15/2011
7888214	Selective stress relaxation of contact etch stop layer through layout design A structure and method of fabrication of a semiconductor device, where a stress layer is formed over a MOS transistor to put either tensile stress or compressive stress on the channel region. The parameters such as the location and area of the contact hole thru the ...	02/15/2011
7883973	Method of forming semiconductor wells A method is provided of forming a semiconductor device. A substrate is provided having a dielectric layer formed thereover. The dielectric layer covers a protected region of the substrate, and has a first opening exposing a first unprotected region of the substrate....	02/08/2011
7875517	Self-aligned complementary LDMOS The invention includes a laterally double-diffused metal-oxide semiconductor (LDMOS) having a reduced size, a high breakdown voltage, and a low on-state resistance. This is achieved by providing a thick gate oxide on the drain side of the device, which reduces elect...	01/25/2011
7871888	Method of manufacturing semiconductor device A p− RESURF region is formed as a surface layer in an n− semiconductor layer. Then, trenches, gate insulating films, and a thick insulating film, gate electrodes, and a gate polysilicon interconnection are formed in this order. Subsequently...	01/18/2011
7863143	High performance schottky-barrier-source asymmetric MOSFETs The present invention, in one embodiment, provides a semiconductor device including a semiconducting body including a schottky barrier region at a first end of the semiconducting body, a drain dopant region at the second end of the semiconducting body, and a channel...	01/04/2011
7851314	Short channel lateral MOSFET and method A short channel Lateral MOSFET (LMOS) and method are disclosed with interpenetrating drain-body protrusions (IDBP) for reducing channel-on resistance while maintaining high punch-through voltage. The LMOS includes lower device bulk layer; upper source and upper drai...	12/14/2010
7824989	Method for reducing overlap capacitance in field effect transistors A method for forming a field effect transistor (FET) device includes forming a gate conductor over a semiconductor substrate; forming a source region, the source region having a source extension that overlaps and extends under the gate conductor; and forming a drain...	11/02/2010
7816214	Coupling well structure for improving HVMOS performance A semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, a cushion region between and ad...	10/19/2010
7790558	Method and apparatus for increase strain effect in a transistor channel Method of enhancing stress in a semiconductor device having a gate stack disposed on a substrate. The method utilizes depositing a nitride film along a surface of the substrate and the gate stack. The nitride film is thicker over a surface of the substrate and thinn...	09/07/2010
7776700	LDMOS device and method An N-channel device (40, 60) is described having a very lightly doped substrate (42) in which spaced-apart P (46) and N (44) wells are provided, whose lateral edges (461, 45) extending to the surface (47). The gate (56	08/17/2010
7745293	Method for manufacturing a thin film transistor including forming impurity regions by diagonal doping It is an object of the present invention to manufacture a thin film transistor having a required property without complicating steps and devices. It is another object of the present invention to provide a technique for manufacturing a semiconductor device having hig...	06/29/2010
7745294	Methods of manufacturing trench isolated drain extended MOS (demos) transistors and integrated circuits therefrom A method of fabricating an integrated circuit (IC) including at least one drain extended MOS (DEMOS) transistor and ICs therefrom includes providing a substrate having a semiconductor surface, the semiconductor surface including at least a first surface region that ...	06/29/2010
7718498	Semiconductor device and method of producing same A semiconductor device suitable for a source-follower circuit, provided with a gate electrode formed on a semiconductor substrate via a gate insulation film, a first conductivity type layer formed in the semiconductor substrate under a conductive portion of the gate...	05/18/2010
7709333	Method for reducing overlap capacitance in field effect transistors A field effect transistor (FET) device includes a gate conductor formed over a semiconductor substrate, a source region having a source extension that overlaps and extends under the gate conductor, and a drain region having a drain extension that overlaps and extend...	05/04/2010
7666745	Method of manufacturing a semiconductor device and a semiconductor device A method of manufacturing a semiconductor device, has forming a gate insulating film over a surface of a substrate, eliminating a portion of the gate insulating film in a region, forming a gate electrode over the gate insulating film and a drain electrode on the reg...	02/23/2010
7638399	Semiconductor device having MOSFET with offset-spacer, and manufacturing method thereof A semiconductor device includes a gate insulating film which is formed on the major surface of a semiconductor substrate, a gate electrode which is formed on the gate insulating film, a first offset-spacer which is formed in contact with one side surface of the gate...	12/29/2009
7608513	Dual gate LDMOS device fabrication methods An N-channel device (40, 60) is described having a lightly doped substrate (42, 42′) in which adjacent or spaced-apart P (46, 46′) and N (44) wells are provided. A lateral isolation wall (76) surrounds at least a portion of the...	10/27/2009
7605040	Method of forming high breakdown voltage low on-resistance lateral DMOS transistor A method of forming a metal oxide semiconductor (MOS) transistor includes the following steps. A substrate of a first conductivity is provided. A first buried layer of a second conductivity type is formed over the substrate. A second buried layer of the first conduc...	10/20/2009
7585735	Asymmetric spacers and asymmetric source/drain extension layers A method of forming a semiconductor device is provided in which a substrate (102) is provided which has a gate dielectric layer (106) disposed thereon, and a gate electrode (116) having first and second sidewalls is formed over the gate dielectr...	09/08/2009
7582533	LDMOS device and method for manufacturing the same Provided is a LDMOS device and method for manufacturing. The LDMOS device includes a second conductive type buried layer formed in a first conductive type substrate. A first conductive type first well is formed in the buried layer and a field insulator with a gate i...	09/01/2009
7579246	Semiconductor device manufacturing method including oblique ion implantation process and reticle pattern forming method An active region and an opposite conductivity active region are formed in a semiconductor substrate. The opposite conductivity active region is covered with a resist pattern. Impurities are implanted into a surface layer of the active region. An angle θ0	08/25/2009

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Class 438/286 - Asymmetric