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| Number | Title | Issue Date |
| 8168501 | Source/drain strained layers A semiconductor device and method of manufacture thereof wherein a PMOS source/drain region of a transistor within the substrate includes a first strained layer in the PMOS source/drain region and a first capping layer in contact with the first strained layer. Furth... | 05/01/2012 |
| 8133789 | Short-channel silicon carbide power mosfet A silicon carbide power MOSFET having a drain region of a first conductivity type, a base region of a second conductivity type above the drain region, and a source region of the first conductivity type adjacent an upper surface of the base region, the base region in... | 03/13/2012 |
| 8105908 | Methods for forming a transistor and modulating channel stress Methods are provided for manufacturing transistors and altering the stress in the channel region of a single transistor. One or more parameters that are effect stress in the channel region are altered for a single transistor to increase or decrease the channel stres... | 01/31/2012 |
| 8084329 | Transistor devices and methods of making In an embodiment, a method of fabricating a transistor device comprises: providing a semiconductor topography comprising a gate conductor disposed above a semiconductor substrate between a pair of dielectric spacers; anisotropically etching exposed regions of the se... | 12/27/2011 |
| 8062946 | Strained channel transistor structure with lattice-mismatched zone and fabrication method thereof A strained-channel transistor structure with lattice-mismatched zone and fabrication method thereof. The transistor structure includes a substrate having a strained channel region, comprising a first semiconductor material with a first natural lattice constant, in a... | 11/22/2011 |
| 8030164 | Compound semiconductor structure A method for manufacturing a compound semiconductor structure, includes (a) selecting a conductive SiC substrate in accordance with color and resistivity and (b) epitaxially growing a GaN series compound semiconductor layer on the selected conductive SiC substrate. ... | 10/04/2011 |
| 8012837 | Method of manufacturing semiconductor device A method of manufacturing a semiconductor device capable of realizing a high yield of a large-scale semiconductor device even when a silicon carbide semiconductor including a defect is used is provided. The method of manufacturing a semiconductor device includes: a ... | 09/06/2011 |
| 8003467 | Method for making a semiconductor device having metal gate stacks The present disclosure provides a method including forming STI features in a silicon substrate, defining a first and a second active regions for a PFET and an NFET, respectively; forming a hard mask having an opening to expose the silicon substrate within the first ... | 08/23/2011 |
| 7994010 | Process for fabricating a semiconductor device having embedded epitaxial regions A process for fabricating a semiconductor device, such as a strained-channel transistor, includes forming epitaxial regions in a substrate in proximity to a gate electrode in which the surface profile of the epitaxial regions is defined by masking sidewall spacers a... | 08/09/2011 |
| 7935601 | Method for providing semiconductors having self-aligned ion implant A method is disclosed that provides a self-aligned nitrogen-implant particularly suited for a Junction Field Effect Transistor (JFET) semiconductor device preferably comprised of a silicon carbide (SiC). This self-aligned nitrogen-implant allows for the realization ... | 05/03/2011 |
| 7910445 | Semiconductor device and method of fabricating the same A method of fabricating a semiconductor device according to one embodiment of the invention includes: forming a gate electrode on a semiconductor substrate through a gate insulating film; forming offset spacers on side surfaces of the gate electrode, respectively; e... | 03/22/2011 |
| 7892927 | Transistor with a channel comprising germanium A transistor including a germanium-rich channel. The germanium-rich channel is produced by oxidation of the silicon contained in the silicon-germanium intermediate layer starting from the lower surface of the said intermediate layer. The germanium atoms are therefor... | 02/22/2011 |
| 7867860 | Strained channel transistor formation A strained channel transistor is provided. The strained channel transistor comprises a substrate formed of a first material. A source region comprised of a second material is formed in a first recess in the substrate, and a drain region comprised of the second mater... | 01/11/2011 |
| 7863141 | Integration for buried epitaxial stressor Structures and methods of fabricating isolation regions for a semiconductor device. An example method comprises the following. We form one or more buried doped regions in a substrate. We form a stressor layer over the substrate. We form a strained layer over the str... | 01/04/2011 |
| 7863142 | Method of forming a germanium silicide layer, semiconductor device including the germanium silicide layer, and method of manufacturing the semiconductor device Example embodiments relate to a method of forming a germanium (Ge) silicide layer, a semiconductor device including the Ge silicide layer, and a method of manufacturing the semiconductor device. A method of forming a Ge silicide layer according to example embodiment... | 01/04/2011 |
| 7851313 | Semiconductor device and process for improved etch control of strained silicon alloy trenches A semiconductor process for improved etch control in which an anisotropic selective etch is used to better control the shape and depth of trenches formed within a semiconductor material. The etchants exhibit preferential etching along at least one of the crystallogr... | 12/14/2010 |
| 7838368 | Nanoscale fet A transistor device is formed of a continuous linear nanostructure having a source region, a drain region and a channel region between the source and drain regions. The source (20) and drain (26) regions are formed of nanowire ania the channel region (... | 11/23/2010 |
| 7811891 | Method to control the gate sidewall profile by graded material composition A semiconductor process and apparatus uses a predetermined sequence of patterning and etching steps to etch a gate stack (30, 32) formed over a substrate (36), thereby forming an etched gate (33) having a vertical sidewall profile (35). B... | 10/12/2010 |
| 7799647 | MOSFET device featuring a superlattice barrier layer and method A method of forming a semiconductor structure includes forming a channel layer; forming a superlattice barrier layer overlying the channel layer, and forming a gate dielectric overlying the superlattice barrier layer. The superlattice barrier layer includes alternat... | 09/21/2010 |
| 7799648 | Method of forming a MOSFET on a strained silicon layer A semiconductor device formed on a strained silicon layer and a method of manufacturing such a semiconductor device are disclosed. In accordance with this invention, a first silicon germanium layer is formed on a single crystalline silicon substrate; a second silico... | 09/21/2010 |
| 7790556 | Integration of high k gate dielectric Methods are provided herein for forming electrode layers over high dielectric constant (“high k”) materials. In the illustrated embodiments, a high k gate dielectric, such as zirconium oxide, is protected from reduction during a subsequent deposition of silicon-... | 09/07/2010 |
| 7790557 | Method of manufacturing silicon carbide semiconductor device Stress is exerted to the SiC crystal in the region, in which the carriers of a SiC semiconductor device flow, to change the crystal lattice intervals of the SiC crystal. Since the degeneration of the conduction bands in the bottoms thereof is dissolved, since the in... | 09/07/2010 |
| 7776698 | Selective formation of silicon carbon epitaxial layer Methods for formation of epitaxial layers containing n-doped silicon are disclosed, including methods for the formation and treatment of epitaxial layers in semiconductor devices, for example, Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices. Forma... | 08/17/2010 |
| 7776697 | Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semi... | 08/17/2010 |
| 7776699 | Strained channel transistor structure and method A transistor device structure comprising: a substrate portion formed from a first material; and a source region, a drain region and a channel region formed in said substrate, the source and drain regions comprising a plurality of islands of a second material differe... | 08/17/2010 |
| 7772071 | Strained channel transistor and method of fabrication thereof The present invention relates to semiconductor integrated circuits. More particularly, but not exclusively, the invention relates to strained channel complimentary metal oxide semiconductor (CMOS) transistor structures and fabrication methods thereof. A strained cha... | 08/10/2010 |
| 7749847 | CMOS integration scheme employing a silicide electrode and a silicide-germanide alloy electrode A p-type field effect transistor (PFET) and an n-type field effect transistor (NFET) are formed by patterning of a gate dielectric layer, a thin silicon layer, and a silicon-germanium alloy layer. After formation of the source/drain regions and gate spacers, silicon... | 07/06/2010 |
| 7704840 | Stress enhanced transistor and methods for its fabrication A stress enhanced MOS transistor and methods for its fabrication are provided. A semiconductor-on-insulator structure is provided which includes a semiconductor layer having a first surface. A strain-inducing epitaxial layer is blanket deposited over the first surfa... | 04/27/2010 |
| 7700447 | Method for making a semiconductor device comprising a lattice matching layer A method for making a semiconductor device which may include forming a first monocrystalline layer comprising a first material having a first lattice constant, a second monocrystalline layer including a second material having a second lattice constant different than... | 04/20/2010 |
| 7687357 | Semiconductor device and method for fabricating the same A method for fabricating a transistor, the method includes forming a gate over a substrate to form a first resultant structure, forming a gate spacer at first and second sidewalls of the gate, etching portions of the substrate proximate to the gate spacer to form a ... | 03/30/2010 |
| 7687356 | Formation of shallow siGe conduction channel A method of forming a silicon germanium conduction channel under a gate stack of a semiconductor device, the gate stack being formed on a silicon layer on an insulating layer, the method including growing a silicon germanium layer over said silicon layer and heating... | 03/30/2010 |
| 7682912 | III-V compound semiconductor device with a surface layer in access regions having charge of polarity opposite to channel charge and method of making the same A method of forming a III-V compound semiconductor structure (10) comprises providing a III-V compound semiconductor substrate including a semi-insulating substrate (12) having at least one epitaxial layer formed thereon and further having a gate insul... | 03/23/2010 |
| 7618866 | Structure and method to form multilayer embedded stressors A multilayer embedded stressor having a graded dopant profile for use in a semiconductor structure for inducing strain on a device channel region is provided. The inventive multilayer stressor is formed within areas of a semiconductor structure in which source/drain... | 11/17/2009 |
| 7598145 | Method for producing SiGebased zones with different contents in Ge on a same substrate by condensation of germanium A method for producing a microelectronic device comprising a plurality of Si1-yGey based semi-conductor zones (wherein 0 | 10/06/2009 |
| 7534687 | Semiconductor device and method for manufacturing the same A semiconductor device, comprises: a transistor having structured to include a gate electrode formed on a semiconductor layer on a semiconductor substrate via a gate insulating film, and a source layer and a drain layer formed on the semiconductor layer sandwiching ... | 05/19/2009 |
| 7514328 | Method for making a semiconductor device including shallow trench isolation (STI) regions with a superlattice therebetween A method for making a semiconductor device may include forming a plurality of shallow trench isolation (STI) regions in a semiconductor substrate. Further, a plurality of layers may be deposited over the substrate to define respective superlattices over the substrat... | 04/07/2009 |
| 7494881 | Methods for selective placement of dislocation arrays Misfit dislocations are selectively placed in layers formed over substrates. Thicknesses of layers may be used to define distances between misfit dislocations and surfaces of layers formed over substrates, as well as placement of misfit dislocations and dislocation ... | 02/24/2009 |
| 7491612 | Field effect transistor with a heterostructure and associated production method A field effect transistor with a heterostructure includes a strained monocrystalline semiconductor layer formed on a carrier material, which has a relaxed monocrystalline semiconductor layer made of a first semiconductor material (Si) as the topmost layer. The strai... | 02/17/2009 |
| 7476590 | Method of manufacturing semiconductor device A method of manufacturing a semiconductor device having: forming a hetero semiconductor layer on at least the major surface of the semiconductor substrate body of a first conductivity type; etching the hetero semiconductor layer selectively by use of a mask layer ha... | 01/13/2009 |
| 7446002 | Method for making a semiconductor device comprising a superlattice dielectric interface layer A method for making a semiconductor device may include forming a superlattice comprising a plurality of stacked groups of layers adjacent a substrate. Each group of layers of the superlattice may include a plurality of stacked base semiconductor monolayers defining ... | 11/04/2008 |
