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| Number | Title | Issue Date |
| 8183116 | Method of manufacturing a double gate transistor A planar double-gate transistor is manufactured wherein crystallisation inhibitors are implanted into the channel region (16) of a semiconductor wafer (10), said wafer having a laminate structure comprising an initial crystalline semiconductor layer ( | 05/22/2012 |
| 8168500 | Double gate depletion mode MOSFET A metal-oxide-semiconductor field effect transistor (MOSFET) has a body layer that follows the contour of exposed surfaces of a semiconductor substrate and contains a bottom surface of a shallow trench and adjoined sidewalls. A bottom electrode layer vertically abut... | 05/01/2012 |
| 8133788 | Method of manufacturing semiconductor device An n type impurity region is provided below a gate electrode. By setting a gate length to be less than a depth of a channel region, a side surface of the channel region and a side surface of the n type impurity region adjacent to the channel region form a substantia... | 03/13/2012 |
| 8124483 | Semiconductor devices and methods of manufacture thereof Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes forming a transistor, the transistor including a fin having a first side and a second side opposite the first... | 02/28/2012 |
| 8105906 | Method for fabricating asymmetric double-gate transistors by which asymmetric and symmetric double-gate transistors can be made on the same substrate A method for fabricating a microelectronic device with one or plural asymmetric double-gate transistors, including: a) forming one or plural structures on a substrate including at least a first semiconducting block configured to form a first gate of a double-gate tr... | 01/31/2012 |
| 8076203 | Semiconductor device and method of manufacturing the same A polysilicon film is formed all over a surface of a semiconductor substrate, then is subject to a CMP process through a mask pattern as a stopper. Then, a metal film is formed all over the resulting surface, and is allowed at least a part of the polysilicon film an... | 12/13/2011 |
| 8076204 | Graphene-based transistor A graphene layer is formed on a surface of a silicon carbide substrate. A dummy gate structure is formed over the fin, in the trench, or on a portion of the planar graphene layer to implant dopants into source and drain regions. The dummy gate structure is thereafte... | 12/13/2011 |
| 8067287 | Asymmetric segmented channel transistors Structures, layouts and methods of forming integrated circuits are described. In various embodiments, the current invention includes an asymmetric segmented transistor. The asymmetric segmented transistor includes a source region and a drain region disposed within a... | 11/29/2011 |
| 8053318 | FET with replacement gate structure and method of fabricating the same A MUGFET and method of manufacturing a MUGFET is shown. The method of manufacturing the MUGFET includes forming temporary spacer gates about a plurality of active regions and depositing a dielectric material over the temporary spacer gates, including between the plu... | 11/08/2011 |
| 8034689 | Method for fabricating a semiconductor device and the semiconductor device made thereof A method for fabricating a semiconductor device and the device made thereof are disclosed. In one aspect, the method includes providing a substrate comprising a semiconductor material. The method further includes patterning at least one fin in the substrate, the fin... | 10/11/2011 |
| 8030163 | Reducing external resistance of a multi-gate device using spacer processing techniques A method includes depositing a sacrificial gate electrode to one or more multi-gate fins. The sacrificial gate electrode is patterned such that it is coupled to a gate region and substantially no sacrificial gate electrode is coupled to source and drain regions. A d... | 10/04/2011 |
| 8003466 | Method of forming multiple fins for a semiconductor device A fabrication process for a FinFET device is provided. The process begins by providing a semiconductor wafer having a layer of conductive material such as silicon. A whole-field arrangement of fins is then formed from the layer of conductive material. The whole-fiel... | 08/23/2011 |
| 7977195 | Method for manufacturing a field effect transistor with auto-aligned grids A method for manufacturing at least one structure for a double grid field effect transistor, including: forming, on an isolating face of a first substrate, a stack comprising successively at least one layer of rear grid material, a layer of rear grid isolator, one s... | 07/12/2011 |
| 7964465 | Transistors having asymmetric strained source/drain portions A structure formation method. First, a structure is provided including (a) a fin region comprising (i) a first source/drain portion having a first surface and a third surface parallel to each other, not coplanar, and both exposed to a surrounding ambient, (ii) a sec... | 06/21/2011 |
| 7960234 | Multiple-gate MOSFET device and associated manufacturing methods One embodiment of the present invention relates to a method of fabricating a multi-gate transistor. During the method a second gate electrode material is selectively removed from a semiconductor structure from which the multi-gate transistor is formed, thereby expos... | 06/14/2011 |
| 7943467 | Structure and method to fabricate MOSFET with short gate A method of producing a semiconducting device is provided that in one embodiment includes providing a semiconducting device including a gate structure atop a substrate, the gate structure including a dual gate conductor including an upper gate conductor and a lower ... | 05/17/2011 |
| 7935599 | Nanowire transistor and method for forming same A method is provided for removing reentrant stringers in the fabrication of a nanowire transistor (NWT). The method provides a cylindrical nanostructure with an outside surface axis overlying a substrate surface. The nanostructure includes an insulated semiconductor... | 05/03/2011 |
| 7935600 | Method of manufacturing multi-channel transistor device and multi-channel transistor device manufactured using the method A multi-channel transistor device and a method of manufacturing the same are provided. The method of a manufacturing a multi-channel transistor device includes defining an active region in a semiconductor substrate by forming an isolation layer exposing an upper sid... | 05/03/2011 |
| 7897468 | Device having self-aligned double gate formed by backside engineering, and device having super-steep retrograded island A method of forming a dual gate semiconductor device is provided that includes providing a substrate having a first semiconductor layer and a second semiconductor layer, in which a first gate structure is formed on the second semiconductor layer. The second semicond... | 03/01/2011 |
| 7883972 | Semiconductor device having a fin structure and method of manufacturing the same A semiconductor device may include a fin structure having source/drain regions and channel fins connected between source/drain patterns. A gate insulation layer may be provided on the channel fins. A gate electrode may include lower gate patterns and an upper gate p... | 02/08/2011 |
| 7879677 | Methods of forming FinFETs and nonvolatile memory devices including FinFETs A FinFET includes a fin that is on a substrate and extends away from the substrate. A device isolation layer is disposed on the substrate on both sides of the fin. An insulating layer is between the fin and the substrate. The insulating layer is directly connected t... | 02/01/2011 |
| 7867859 | Gate electrode with depletion suppression and tunable workfunction Semiconductor device performance is improved via a gate structure having a tunable effective workfunction and reduced gate depletion effects. According to an example embodiment, the design threshold voltage of a semiconductor device is adjusted in a manner that incl... | 01/11/2011 |
| 7842576 | Semiconductor device including first and second sidewalls and method of manufacturing semiconductor device The invention provides a method of manufacturing a semiconductor device including a non-volatile memory with high yield, and a semiconductor device manufactured by the method. A method of manufacturing a semiconductor device includes a process of forming a second si... | 11/30/2010 |
| 7838367 | Method for the manufacture of a semiconductor device and a semiconductor device obtained through it The invention relates to a semiconductor device (10) having a semiconductor body (2), comprising a field effect transistor, a first gate dielectric (6A) being formed on a first surface at the location of the channel region (5) and on it a... | 11/23/2010 |
| 7820513 | Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication A nonplanar semiconductor device and its method of fabrication is described. The nonplanar semiconductor device includes a semiconductor body having a top surface opposite a bottom surface formed above an insulating substrate wherein the semiconductor body has a pai... | 10/26/2010 |
| 7816213 | Semiconductor device having transistors each having gate electrode of different metal ratio and production process thereof A semiconductor device with integrated MIS field-effect transistors includes a first transistor containing a first gate electrode having a composition represented by MAx and a second transistor containing a second gate electrode having a composition represented by M... | 10/19/2010 |
| 7767532 | Method for manufacturing an EEPROM cell A method for manufacturing an EEPROM cell including a dual-gate MOS transistor. The method includes the steps of providing a semiconductor substrate covered with a stack of first and second layers, forming at least one first opening in the second layer, forming, in ... | 08/03/2010 |
| 7741182 | Method of fabricating a dual gate FET The invention provides a method of fabricating an extremely short-length dual-gate FET, using conventional semi-conductor processing techniques, with extremely small and reproducible fins with a pitch and a width that are both smaller than can be obtained with photo... | 06/22/2010 |
| 7723193 | Method of forming an at least penta-sided-channel type of FinFET transistor An at least penta-sided-channel type of FinFET transistor may include: a base; a semiconductor body formed on the base, the body being arranged in a long dimension to have source/drain regions sandwiching a channel region, at least the channel, in cross-section tran... | 05/25/2010 |
| 7709332 | Process for fabricating a field-effect transistor with self-aligned gates A first gate, formed on a substrate, is surmounted by a hard layer designed, with first spacers surrounding the first gate, to act as etching mask to bound the channel and a pad that bounds a space subsequently used to form a gate cavity. The hard layer is preferabl... | 05/04/2010 |
| 7704838 | Method for forming an independent bottom gate connection for buried interconnection including bottom gate of a planar double gate MOSFET A method is provided for making a semiconductor device, which comprises (a) providing a semiconductor structure comprising a top gate (228) and a bottom gate (240); (b) creating first, second and third openings in the semiconductor structure, wherein t... | 04/27/2010 |
| 7704839 | Buried stress isolation for high-performance CMOS technology A field effect transistor (FET) comprises a substrate; a buried oxide (BOX) layer over the substrate; a current channel region over the BOX layer; source/drain regions adjacent to the current channel region; a buried high-stress film in the BOX layer and regions of ... | 04/27/2010 |
| 7700446 | Virtual body-contacted trigate A field effect transistor (FET) and method of forming the FET comprises a substrate; a silicon germanium (SiGe) layer over the substrate; a semiconductor layer over and adjacent to the SiGe layer; an insulating layer adjacent to the substrate, the SiGe layer, and th... | 04/20/2010 |
| 7700445 | Method for fabricating multiple FETs of different types For fabricating multiple field effect transistors (FETs), a first conductive layer is deposited over first and second active regions of a semiconductor substrate. The first conductive layer is patterned over the second active region to form mold structures. Mask str... | 04/20/2010 |
| 7687355 | Method for manufacturing fin transistor that prevents etching loss of a spin-on-glass insulation layer A method for manufacturing a fin transistor includes forming a trench by etching a semiconductor substrate. A flowable insulation layer is filled in the trench to form a field insulation layer defining an active region. The portion of the flowable insulation layer c... | 03/30/2010 |
| 7682911 | Semiconductor device having a fin transistor and method for fabricating the same A fin transistor includes fin active region, an isolation layer covering both sidewalls of a lower portion of the fin active region, a gate insulation layer disposed over a surface of the fin active region, and a gate electrode disposed over the gate insulation laye... | 03/23/2010 |
| 7670912 | Methods of fabricating multichannel metal oxide semiconductor (MOS) transistors Unit cells of metal oxide semiconductor (MOS) transistors are provided including an integrated circuit substrate an a MOS transistor on the integrated circuit substrate. The MOS transistor includes a source region, a drain region and a gate. The gate is positioned b... | 03/02/2010 |
| 7659169 | Semiconductor device and method of manufacturing thereof There is a method of manufacturing a semiconductor device with a dual gate field effect transistor, the method including a semiconductor body a semiconductor material having a surface with a source region and a drain region of a first conductivity type and with a ch... | 02/09/2010 |
| 7648880 | Nitride-encapsulated FET (NNCFET) A double-gate field effect transistor (DGFET) structure and method of forming such a structure in which the parasitic capacitance under the source/drain regions is substantially reduced are provided. In the present invention, self-aligned isolation regions are provi... | 01/19/2010 |
| 7635632 | Gate electrode for a semiconductor fin device A method for forming a gate electrode for a multiple gate transistor provides a doped, planarized gate electrode material which may be patterned using conventional methods to produce a gate electrode that straddles the active area of the multiple gate transistor and... | 12/22/2009 |
