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| Number | Title | Issue Date |
| 8178411 | Method for producing a stop zone in a semiconductor body and semiconductor component having a stop zone A method for producing a buried stop zone in a semiconductor body and a semiconductor component having a stop zone, the method including providing a semiconductor body having a first and a second side and a basic doping of a first conduction type. The method further... | 05/15/2012 |
| 8097515 | Self-aligned contacts for nanowire field effect transistors A method for forming a nanowire field effect transistor (FET) device includes forming a nanowire over a semiconductor substrate, forming a gate structure around a portion of the nanowire, forming a capping layer on the gate structure; forming a first spacer adjacent... | 01/17/2012 |
| 8048745 | Transistor and method of fabricating the same Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device can include a transistor structure including a gate electrode and a first channel region and source/drain regions on a substrate, and a second channel region and sour... | 11/01/2011 |
| 8034688 | Methods of forming power switching semiconductor devices including rectifying junction-shunts A semiconductor device includes a drift layer having a first conductivity type and a body region adjacent the drift layer. The body region has a second conductivity type opposite the first conductivity type and forms a p-n junction with the drift layer. The device f... | 10/11/2011 |
| 7687354 | Fabrication of a semiconductor device with stressor In a semiconductor fabrication process, an epitaxial layer is formed overlying a substrate, wherein there is a lattice mismatch between the epitaxial layer and the substrate. A hard mask having an opening is formed overlying the epitaxial layer. A recess is formed t... | 03/30/2010 |
| 7638397 | Method of forming quantum wire gate device The present invention relates to a method of forming a quantum wire gate device. The method includes patterning a first oxide upon a substrate. Preferably the first oxide pattern is precisely and uniformly spaced to maximize quantum wire numbers per unit area. The m... | 12/29/2009 |
| 7534685 | Method for fabrication of a capacitor, and a monolithically integrated circuit comprising such a capacitor A method for fabrication of a monolithically integrated SOI substrate capacitor has the steps of: forming an insulating trench (14), which reaches down to the insulator (11) and surrounds a region (13′) of the monocrystalline silicon (13 | 05/19/2009 |
| 7494880 | Method of manufacturing semiconductor device An oxide film is formed on an SOI layer, an isolation oxide film and a gate electrode. A nitride film is formed on the oxide film. Next, anisotropic etching is performed only on the nitride film to form sidewalls on opposite side surfaces of the gate electrode. Thus... | 02/24/2009 |
| 7491611 | Method and apparatus for controlling a circuit with a high voltage sense device A control circuit with a high voltage sense device. In one embodiment, a circuit includes a first transistor disposed in a first substrate having first, second and third terminals. A first terminal of the first transistor is coupled to an external voltage. A voltage... | 02/17/2009 |
| 7435637 | Quantum wire gate device and method of making same The present invention relates to a method of forming a quantum wire gate device. The method includes patterning a first oxide upon a substrate. Preferably the first oxide pattern is precisely and uniformly spaced to maximize quantum wire numbers per unit area. The m... | 10/14/2008 |
| 7402483 | Methods of forming a multi-bridge-channel MOSFET A multi-bridge-channel MOSFET (MBCFET) may be formed by forming a stacked structure on a substrate that includes channel layers and interchannel layers interposed between the channel layers. Trenches are formed by selectively etching the stacked structure. The trenc... | 07/22/2008 |
| 7391098 | Semiconductor substrate, semiconductor device and method of manufacturing the same The present invention relates to a semiconductor substrate, a semiconductor device with high carrier mobility and a method of manufacturing the same. According to the present invention, there are provided a semiconductor substrate comprising a silicon substrate, a s... | 06/24/2008 |
| 7361556 | Method of fabricating semiconductor side wall fin A double gated silicon-on-insulator (SOI) MOSFET is fabricated by forming epitaxially grown channels, followed by a damascene gate. The double gated MOSFET features narrow channels, which increases current drive per layout width and provides low out conductance.... | 04/22/2008 |
| 7361565 | Method of forming a metal gate in a semiconductor device In a method of forming a metal gate in a semiconductor device, a gate insulation pattern and a dummy gate pattern are formed on a substrate. An insulation interlayer is formed on the dummy gate pattern to cover the dummy gate pattern. The insulation interlayer is po... | 04/22/2008 |
| 7361973 | Embedded stressed nitride liners for CMOS performance improvement The present invention provides a semiconducting device including a gate region positioned on a mesa portion of a substrate; and a nitride liner positioned on the gate region and recessed surfaces of the substrate adjacent to the gate region, the nitride liner provid... | 04/22/2008 |
| 7351622 | Methods of forming semiconductor device A method of forming a semiconductor device includes forming a three-dimensional structure formed of a semiconductor on a semiconductor substrate, and isotropically doping the three-dimensional structure by performing a plasma doping process using a first source gas ... | 04/01/2008 |
| 7344947 | Methods of performance improvement of HVMOS devices Methods fabricate DEMOS devices having varied channel lengths and substantially similar threshold voltages. A threshold voltage is selected for first and second devices. First and second well regions are formed. First and second drain extension regions are formed wi... | 03/18/2008 |
| 7341916 | Self-aligned nanometer-level transistor defined without lithography A field effect transistor (FET) device structure and method for forming FETs for scaled semiconductor devices. Specifically, FinFET devices are fabricated from silicon-on-insulator (SOI) wafers in a highly uniform and reproducible manner. The method facilitates form... | 03/11/2008 |
| 7338873 | Method of fabricating a field effect transistor structure with abrupt source/drain junctions Microelectronic structures embodying the present invention include a field effect transistor (FET) having highly conductive source/drain extensions. Formation of such highly conductive source/drain extensions includes forming a passivated recess which is back filled... | 03/04/2008 |
| 7335945 | Multi-gate MOS transistor and method of manufacturing the same Provided are a multi-gate MOS transistor and a method of manufacturing the same. Two silicon fins are vertically stacked on a silicon on insulator (SOI) substrate, and four side surfaces of an upper silicon fin and three side surfaces of a lower silicon fin are used... | 02/26/2008 |
| 7326619 | Method of manufacturing integrated circuit device including recessed channel transistor A method according to some embodiments of the invention includes defining an active region by forming a trench device isolation region on an integrated substrate, forming a mask pattern that exposes a channel sub-region of the active region and the trench device iso... | 02/05/2008 |
| 7323390 | Semiconductor device and method for production thereof The semiconductor device according to the invention includes a substrate, a field insulating region which delimits an active region of the semiconductor substrate, a collector, at least one collector contact region associated with the collector, and a base with an a... | 01/29/2008 |
| 7320919 | Method for fabricating semiconductor device with metal-polycide gate and recessed channel A method for fabricating a semiconductor device with a metal-polycide gate and a recessed channel, including the steps of: forming trenches for a recessed channel in an active area of a semiconductor substrate; forming a gate insulating layer on the semiconductor su... | 01/22/2008 |
| 7314801 | Semiconductor device having a surface conducting channel and method of forming A semiconductor device including a metal oxide layer, a channel area of the metal oxide layer, a preservation layer formed on the channel area of the metal oxide layer, and at least two channel contacts coupled to the channel area of the metal oxide layer, and a met... | 01/01/2008 |
| 7312125 | Fully depleted strained semiconductor on insulator transistor and method of making the same An integrated circuit includes multiple layers. A semiconductor-on-insulator (SOI) wafer can be used to house transistors. Two substrates or wafers can be bonded to form the multiple layers. A strained semiconductor layer can be between a silicon germanium layer and... | 12/25/2007 |
| 7306993 | Method for fabricating semiconductor device with recessed channel A method for fabricating a semiconductor device with a recessed channel, including the steps of: forming trenches for a recessed channel in an active area of a semiconductor substrate; forming a gate insulating layer on the semiconductor substrate having the trenche... | 12/11/2007 |
| 7304368 | Chalcogenide-based electrokinetic memory element and method of forming the same Memory elements including a first electrode and a second electrode. A chalcogenide material layer is between the first and second electrodes and a tin-chalcogenide layer is between the chalcogenide material layer and the second electrode. A selenide layer is between... | 12/04/2007 |
| 7301180 | Structure and method for a high-speed semiconductor device having a Ge channel layer The invention provides semiconductor structure comprising a strained Ge channel layer, and a gate dielectric disposed over the strained Ge channel layer. In one aspect of the invention, a strained Ge channel MOSFET is provided. The strained Ge channel MOSFET include... | 11/27/2007 |
| 7288828 | Metal oxide semiconductor transistor device A metal-oxide-semiconductor (MOS) transistor device is provided. The MOS transistor device includes a substrate, a gate structure, a spacer, a source/drain region and a barrier layer. The gate structure is disposed on the substrate. The gate structure includes a gat... | 10/30/2007 |
| 7282401 | Method and apparatus for a self-aligned recessed access device (RAD) transistor gate A method used in fabrication of a recessed access device transistor gate has increased tolerance for mask misalignment. One embodiment of the invention comprises forming a vertical spacing layer over a semiconductor wafer, then etching the vertical spacing layer and... | 10/16/2007 |
| 7279387 | Method for fabricating asymmetric semiconductor device A method for fabricating an asymmetric semiconductor device is provided. A substrate formed with at least one base structure of MOSFET thereon is provided, wherein the base structure includes a gate over the substrate and a source extension and a drain extension in ... | 10/09/2007 |
| 7268045 | N-channel LDMOS with buried P-type region to prevent parasitic bipolar effects An improved n-channel integrated lateral DMOS (10) in which a buried body region (30), beneath and self-aligned to the source (18) and normal body diffusions, provides a low impedance path for holes emitted at the drain region (16). This ... | 09/11/2007 |
| 7265416 | High breakdown voltage low on-resistance lateral DMOS transistor In accordance with the present invention, a metal oxide semiconductor (MOS) transistor has a substrate of a first conductivity type. A drift region of a second conductivity type extends over the substrate. A body region of the first conductivity type is in the drift... | 09/04/2007 |
| 7265427 | Semiconductor apparatus and method of manufacturing the semiconductor apparatus A semiconductor apparatus wherein a device formed on a semiconductor substrate comprises a gate insulating film including a high dielectric constant film formed on the substrate and an anti-reaction film formed on the high dielectric constant film, and a gate electr... | 09/04/2007 |
| 7256464 | Metal oxide semiconductor transistor and fabrication method thereof A metal oxide semiconductor transistor comprising a first doping type substrate, an isolation layer, a plurality of gates, a masking layer, a gate oxide layer, a plurality of second doping type source/drain regions and spacers. The first doping type substrate has a ... | 08/14/2007 |
| 7253060 | Gate-all-around type of semiconductor device and method of fabricating the same A gate-all-around (GAA) transistor device has a pair of pillars that include the source/drain regions, a channel region bridging the source/drain regions, and a gate electrode and gate oxide which surround the channel region. The pillars are formed by providing a mo... | 08/07/2007 |
| 7247569 | Ultra-thin Si MOSFET device structure and method of manufacture The present invention comprises a method for forming an ultra-thin channel MOSFET and the ultra-thin channel MOSFET produced therefrom. Specifically, the method comprises providing an SOI substrate having a buried insulating layer underlying an SOI layer; forming a ... | 07/24/2007 |
| 7244654 | Drive current improvement from recessed SiGe incorporation close to gate A method (100) of forming a transistor includes forming a gate structure (106, 108) over a semiconductor body and forming recesses (112) substantially aligned to the gate structure in the semiconductor body. Silicon germanium is then epitaxially... | 07/17/2007 |
| 7238985 | Trench type mosgated device with strained layer on trench sidewall A MOSgated trench device has a reduced on resistance by forming a less than about a 13 nm thick strained SiGe layer on the silicon surface of the trenches and forming a thin (30 nm or less) layer of epitaxially deposited silicon on the SiGe layer which epi layer is ... | 07/03/2007 |
| 7224007 | Multi-channel transistor with tunable hot carrier effect A multiple channel transistor provides a transistor with an improved drive current and speed by using tunable hot carrier effects. A thin gate oxide has a carrier confinement layer formed on top thereof. Holes produced by hot carrier effects are retained by the carr... | 05/29/2007 |
