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| Number | Title | Issue Date |
| 7892926 | Fuse link structures using film stress for programming and methods of manufacture A method of forming a programmable fuse structure includes forming at least one shallow trench isolation (STI) in a substrate, forming an e-fuse over the at least one STI and depositing an interlevel dielectric (ILD) layer over the e-fuse. Additionally, the method i... | 02/22/2011 |
| 7659168 | eFuse and methods of manufacturing the same In a first aspect, a first apparatus is provided. The first apparatus is an eFuse including (1) a semiconducting layer above an insulating oxide layer of a substrate; (2) a diode formed in the semiconducting layer; and (3) a silicide layer formed on the diode. Numer... | 02/09/2010 |
| 7560345 | Method of assessing potential for charging damage in integrated circuit designs and structures for preventing charging damage A method for preventing charging damage during manufacturing of an integrated circuit design, having silicon over insulator (SOI) transistors. The method prevents damage from charging during processing to the gate of IC devices by assigning regions to the IC design ... | 07/14/2009 |
| 7517763 | Semiconductor device having fuse and capacitor at the same level and method of fabricating the same In a semiconductor device and a method of fabricating the same, a fuse and a capacitor are formed at a same level on a semiconductor substrate having a fuse area and a capacitor area. The fuse is placed on the fuse area, and a lower plate is placed on the capacitor ... | 04/14/2009 |
| 7517762 | Semiconductor device capable of preventing moisture-absorption of fuse area thereof and method for manufacturing the fuse area A fuse area of a semiconductor device capable of preventing moisture-absorption and a method for manufacturing the fuse area are provided. When forming a guard ring for preventing permeation of moisture through the sidewall of an exposed fuse opening portion, an etc... | 04/14/2009 |
| 7470590 | Methods of forming semiconductor constructions The invention includes methods by which a fuse box of a semiconductor construction is fabricated to have a substantially uniform layer over fuses extending therein. In particular aspects, the invention includes methods in which one or more processing steps associate... | 12/30/2008 |
| 7442596 | Methods of manufacturing fin type field effect transistors A fin type field effect transistor includes a semiconductor substrate, an active fin, a first hard mask layer pattern, a gate insulation layer pattern, a first conductive layer pattern, and source/drain regions. The active fin includes a semiconductor material and i... | 10/28/2008 |
| 7442626 | Rectangular contact used as a low voltage fuse element A repair fuse element and method of construction are disclosed that eliminate or substantially reduce the disadvantages and problems associated with prior fuse elements. In one embodiment, the fuse element is constructed with a rectangular-shaped contact. The contac... | 10/28/2008 |
| 7413936 | Method of forming copper layers A programmable package with a fuse embedded therein, and fabrication method are provided. The fuse has first and second terminal ends joined by a central portion defining a fusible link. The ends include a portion of the first and second conductive layers, the centr... | 08/19/2008 |
| 7402464 | Fuse box of semiconductor device and fabrication method thereof A fuse box includes a semiconductor substrate having a fuse region, and a lower line in the fuse region that has a first region and a second region. An upper line is placed on the upper part of the lower line to overlap the first region. A fuse is placed on the uppe... | 07/22/2008 |
| 7402887 | Semiconductor device having fuse area surrounded by protection means A semiconductor device has a semiconductor substrate, first and second insulating layers, a fuse, a diffusion layer and a conductive pattern. The first insulating layer is selectively formed on a surface of the semiconductor substrate. The fuse is formed on the firs... | 07/22/2008 |
| 7387937 | Thermal dissipation structures for FinFETs A fin-type field effect transistor has an insulator layer above a substrate and a fin extending above the insulator layer. The fin has a channel region, and source and drain regions. A gate conductor is positioned over the channel region. The insulator layer include... | 06/17/2008 |
| 7381594 | CMOS compatible shallow-trench efuse structure and method A semiconductor structure including at least one e-fuse embedded within a trench that is located in a semiconductor substrate (bulk or semiconductor-on-insulator) is provided. In accordance with the present invention, the e-fuse is in electrical contact with a dopan... | 06/03/2008 |
| 7354805 | Method of making electrically programmable fuse for silicon-on-insulator (SOI) technology A fuse structure and method of forming the same is described, wherein the body of the fuse is formed from a crystalline semiconductor body on an insulator, preferably of a silicon-on-insulator wafer, surrounded by a fill-in dielectric. The fill-in dielectric is pref... | 04/08/2008 |
| 7352050 | Fuse region of a semiconductor region In a fuse region of a semiconductor device, and a method of fabricating the same, the fuse region includes an interlayer insulating layer on a semiconductor substrate, a plurality of fuses on the interlayer insulating layer disposed in parallel with each other, a bl... | 04/01/2008 |
| 7338888 | Method for manufacturing a semiconductor device having a silicided gate electrode and a method for manufacturing an integrated circuit including the same The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit including the semiconductor device. The method for manufacturing the semiconductor device (100), among other possible steps, ... | 03/04/2008 |
| 7340360 | Method for determining projected lifetime of semiconductor devices with analytical extension of stress voltage window by scaling of oxide thickness A method for efficiently and accurately measuring a maximum Vcc calculation or failure rate and lifetime projection for microprocessors and other semiconductor products analytically scales low voltages applied to thinner oxides to thicker oxides. The expa... | 03/04/2008 |
| 7335537 | Method of manufacturing semiconductor device including bonding pad and fuse elements A method of manufacturing a semiconductor device includes forming a first insulating film supported by a semiconductor substrate, forming an aluminum layer supported by the first insulating film, etching the aluminum layer to form a bonding pad and fuse elements, de... | 02/26/2008 |
| 7323389 | Method of forming a FINFET structure A semiconductor device (10) such as a FinFET transistor of small dimensions is formed in a process that permits substantially uniform ion implanting (32) of a source (14) electrode and a drain (16) electrode adjacent to an intervening gat... | 01/29/2008 |
| 7314794 | Low-cost high-performance planar back-gate CMOS A method of fabricating a high-performance planar back-gate CMOS structure having superior short-channel characteristics and reduced capacitance using processing steps that are not too lengthy or costly is provided. Also provided is a high-performance planar back-ga... | 01/01/2008 |
| 7314815 | Manufacturing method of one-time programmable read only memory An one-time programmable read only memory is provided. An N-type doping region and a first P-type doping layer are disposed in a P-type semiconductor substrate sequentially. A second P-type doping layer is disposed between the first P-type doping layer and the N-typ... | 01/01/2008 |
| 7312125 | Fully depleted strained semiconductor on insulator transistor and method of making the same An integrated circuit includes multiple layers. A semiconductor-on-insulator (SOI) wafer can be used to house transistors. Two substrates or wafers can be bonded to form the multiple layers. A strained semiconductor layer can be between a silicon germanium layer and... | 12/25/2007 |
| 7306998 | Formation of abrupt junctions in devices by using silicide growth dopant snowplow effect A method of forming an abrupt junction device with a semiconductor substrate is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed on the gate dielectric. A sidewall spacer is formed on the semiconductor substrate adjacent the g... | 12/11/2007 |
| 7268047 | Semiconductor device and method for manufacturing the same A gate insulating film on a silicon substrate of includes a SiO2 film and a high-k film. The high-k film contains a transition metal, aluminum, silicon, and oxygen. The concentration of silicon in the high-k film is higher than the concentrations of the t... | 09/11/2007 |
| 7267430 | Heater chip for inkjet printhead with electrostatic discharge protection An inkjet printhead heater chip includes a resistor layer, a dielectric layer on the resistor layer and a cavitation layer on the dielectric layer. A grounded-gate MOSFET electrically attaches to the cavitation layer to protect the dielectric layer from breakdown du... | 09/11/2007 |
| 7256445 | Fabrication of an EEPROM cell with emitter-polysilicon source/drain regions An EEPROM memory cell uses an emitter polysilicon film for fabricating shallow source/drain regions to increase a breakdown voltage of the wells. The wells are fabricated to be approximately 100 nm (0.1 micrometers (μm)) in depth with a breakdown voltage of approxi... | 08/14/2007 |
| 7253033 | Method of manufacturing a semiconductor device that includes implanting in multiple directions a high concentration region In a complete depletion type SOI transistor, the roll-off of a threshold value is suppressed, independently from the formation of an SOI film to be thinner. As for a semiconductor device (1), the impurity concentration in a channel formation portion (10 | 08/07/2007 |
| 7250666 | Schottky barrier diode and method of forming a Schottky barrier diode Disclosed is a silicon-on-insulator-based Schottky barrier diode with a low forward voltage that can be manufactured according to standard SOI process flow. An active silicon island is formed using an SOI wafer. One area of the island is heavily-doped with an n-type... | 07/31/2007 |
| 7251403 | Light scattering structures formed in silicon waveguides In a standard CMOS process, a layer of metallic salicide can be deposited on those selected portions of an integrated circuit, where it is desired to have metallic contacts for electronic components, such as transistors. The deposition of a salicide into optical ele... | 07/31/2007 |
| 7250361 | Method for forming a bonding pad of a semiconductor device including a plasma treatment Disclosed is a method for forming a bonding pad of a semiconductor device. The present invention provides a method for forming a bonding pad of a semiconductor device comprising the steps of: (a) forming a top metal line having a predetermined width on a structure o... | 07/31/2007 |
| 7242558 | ESD protection module triggered by BJT punch-through An electrostatic discharge protection (ESD) circuit is disclosed for protecting a pad of an integrated circuit from ESD events. The ESD circuit has an ESD trigger module having a first and second transistors connected in series, between the pad and a first common no... | 07/10/2007 |
| 7242072 | Electrically programmable fuse for silicon-on-insulator (SOI) technology A fuse structure and method of forming the same is described, wherein the body of the fuse is formed from a crystalline semiconductor body on an insulator, preferably of a silicon-on-insulator wafer, surrounded by a fill-in dielectric. The fill-in dielectric is pref... | 07/10/2007 |
| 7238988 | Semiconductor memory device A silicide film is provided in diffusion regions formed in a semiconductor layer. The silicide film has a thickness substantially same as that of the semiconductor layer. The silicide film has the bottom located in the vicinity of an interface between the insulator ... | 07/03/2007 |
| 7220635 | Method for making a semiconductor device with a metal gate electrode that is formed on an annealed high-k gate dielectric layer A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer on a substrate, and forming a sacrificial layer on the high-k gate dielectric layer. After etching the sacrificial layer, first and second spacers a... | 05/22/2007 |
| 7199032 | Metal silicide induced lateral excessive encroachment reduction by silicon <110> channel stuffing The present invention provides a method of manufacturing a metal silicide electrode (100) for a semiconductor device (110). The method comprises implanting small atoms into an nMOS semiconductor substrate (130) to a depth (132) no greater... | 04/03/2007 |
| 7118951 | Method of isolating the current sense on power devices while maintaining a continuous stripe cell An integrated circuit die includes an active area having source dopants and contacts. An active area metal layer overlies the active area. A sense area is disposed on the die. A sense area metal layer overlies the sense area. A plurality of polysilicon gate stripes,... | 10/10/2006 |
| 7092273 | Low voltage non-volatile memory transistor A p-channel non-volatile memory (NVM) transistor is programmed by shifting the threshold voltage of the transistor. The threshold voltage is shifted by introducing a programming current to the gate electrode of the transistor, and simultaneously introducing a negati... | 08/15/2006 |
| 7087974 | Semiconductor integrated circuit including anti-fuse and method for manufacturing the same An anti-fuse is manufactured by forming an isolation region including an insulating material layer buried in a surface of a device formation region on a surface of a semiconductor substrate, and by forming diffusion regions at both sides of the isolation region, the... | 08/08/2006 |
| 7075127 | Single-poly 2-transistor based fuse element An electrically programmable transistor fuse having a double-gate arrangement disposed in a single layer of polysilicon in which a first gate is disposed overlapping a portion of a source region and a second gate is insulated from the first gate and disposed overlap... | 07/11/2006 |
| 7071534 | Antifuse structure and method of use An antifuse structure and method of use are disclosed. According to one embodiment of the present invention a first programming voltage is coupled to a well of a first conductivity type in a substrate of a second conductivity type in an antifuse. A second programmin... | 07/04/2006 |
