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| Number | Title | Issue Date |
| 7964464 | Semiconductor device and method of manufacturing the same A device isolation film is formed in a semiconductor substrate at a border portion between a first region and a second region for defining a first active region in the first region and a second active region in the second region. A gate insulating film and a gate el... | 06/21/2011 |
| 7799645 | Semiconductor device and method of manufacturing the same An embodiment of a semiconductor device includes a substrate including a cell region and a peripheral region; a cell gate pattern on the cell region; and a peripheral gate pattern on the peripheral region, wherein a first cell insulation layer, a second cell insulat... | 09/21/2010 |
| 7795097 | Semiconductor device manufactured by removing sidewalls during replacement gate integration scheme One aspect of the invention provides a semiconductor device that includes gate electrodes comprising a metal or metal alloy located over a semiconductor substrate, wherein the gate electrodes are free of spacer sidewalls. The device further includes source/drains ha... | 09/14/2010 |
| 7713824 | Small feature integrated circuit fabrication A method for controlling etching during photolithography in the fabrication of an integrated circuit in connection with first and second features that are formed on the integrated circuit having a gap there between comprising depositing a layer of photoresist on the... | 05/11/2010 |
| 7588987 | Semiconductor device and method for fabricating the same A semiconductor device and a method for fabricating the same selectively forms a nitride layer having high tensile stress in an NMOS transistor area, to thereby form a strained-silicon structure in an NMOS channel region, whereby electron mobility is improved and dr... | 09/15/2009 |
| 7442610 | Low thermal budget fabrication method for a mask read only memory device A low thermal budget fabrication method for a mask ROM is described. The method includes providing a substrate having a gate oxide layer thereon. A first conductive layer is formed on the gate oxide layer. A plurality of bit lines is formed in the substrate. A secon... | 10/28/2008 |
| 7396727 | Transistor of semiconductor device and method for fabricating the same A transistor which may effectively control the short channel effect with a vertical transistor structure. This structure may prevent the degradation of a transistor's performance caused by the hot carrier effect. The transistor has a source region having a concentra... | 07/08/2008 |
| 7393737 | Semiconductor device and a method of manufacturing the same A semiconductor device which, in spite of the existence of a dummy active region, eliminates the need for a larger chip area and improves the surface flatness of the semiconductor substrate. In the process of manufacturing it, a thick gate insulating film for a high... | 07/01/2008 |
| 7371667 | Semiconductor device and method of fabricating same There are disclosed TFTs that have excellent characteristics and can be fabricated with a high yield. The TFTs are fabricated, using an active layer crystallized by making use of nickel. Gate electrodes are comprising tantalum. Phosphorus is introduced into source/d... | 05/13/2008 |
| 7364951 | Nonvolatile semiconductor memory device and method for manufacturing the same A method for manufacturing a nonvolatile semiconductor memory device having a step of forming a first gate electrode on a peripheral circuit portion and a second gate electrode on a memory cell portion, a step of introducing impurity into the peripheral circuit port... | 04/29/2008 |
| 7364973 | Method of manufacturing NOR-type mask ROM device and semiconductor device including the same A method of manufacturing a NOR-type mask ROM device includes forming a first gate electrode for an OFF cell and a second gate electrode for an ON cell on a semiconductor substrate of a first conductivity type. To code the mask ROM device, a plurality of source/drai... | 04/29/2008 |
| 7352046 | Semiconductor integrated circuit device A semiconductor integrated circuit device has a first MOS transistor having an insulating film, a first source, a first gate electrode, and a nitride film overlapping the first gate electrode from the first source through the insulating film. A second MOS transistor... | 04/01/2008 |
| 7344951 | Surface preparation method for selective and non-selective epitaxial growth According to one embodiment of the invention, a surface preparation method for selective and non-selective epitaxial growth includes providing a substrate having a gate region, a source region, and a drain region, etching a first portion of the source region and the... | 03/18/2008 |
| 7339223 | Semiconductor devices having dual capping layer patterns and methods of manufacturing the same Some embodiments provide a semiconductor substrate having a cell array region and a peripheral circuit region. A plurality of word line patterns are placed in the cell array region, each of which include a word line and a word line capping layer pattern stacked ther... | 03/04/2008 |
| 7335543 | MOS device for high voltage operation and method of manufacture A high voltage semiconductor device. The high voltage device has a substrate (e.g., silicon wafer) having a surface region. The substrate has a well region within the substrate and a double diffused drain region within the well region. A gate dielectric layer is ove... | 02/26/2008 |
| 7320917 | Semiconductor device and method for manufacturing the same Gate length is 110 nm±15 nm or shorter (130 nm or shorter in a design rule) or an aspect ratio of an area between adjacent gate electrode structures thereof (ratio of the height of the gate electrode structure to the distance between the gate electrode structures) ... | 01/22/2008 |
| 7321146 | DRAM memory cell and method of manufacturing the same A DRAM memory cell includes a semiconductor substrate, an interlayer dielectric having storage node contact plugs that is formed on the semiconductor substrate, and storage node electrodes that are formed on the interlayer dielectric to contact the storage node cont... | 01/22/2008 |
| 7300842 | Method of fabricating a mask ROM A mask ROM and fabrication method thereof are disclosed, in which a bit line is formed of a conductive material such as polysilicon, by which a device size can be minimized, and by which resistance characteristics are enhanced. ... | 11/27/2007 |
| 7276762 | NROM flash memory devices on ultrathin silicon An NROM flash memory cell is implemented in an ultra-thin silicon-on-insulator structure. In a planar device, the channel between the source/drain areas is normally fully depleted. An oxide layer provides an insulation layer between the source/drain areas and the ga... | 10/02/2007 |
| 7271063 | Method of forming FLASH cell array having reduced word line pitch A method of forming a NAND Flash memory device includes forming a control gate polysilicon layer over a substrate, forming a mask layer over the control gate polysilicon layer, the mask layer including a mask pattern defining a plurality of spaced word lines of the ... | 09/18/2007 |
| 7265012 | Formation of standard voltage threshold and low voltage threshold MOSFET devices Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within... | 09/04/2007 |
| 7265435 | Method for implanting atomic species through an uneven surface of a semiconductor layer A method for implanting atomic species through an uneven surface of a semiconductor layer. The technique includes applying a covering layer upon the uneven surface in an amount sufficient and in a manner to increase surface uniformity. The method also includes impla... | 09/04/2007 |
| 7259070 | Semiconductor devices and methods for fabricating the same Disclosed are semiconductor devices and methods for fabricating the same. According to one embodiment, the method includes sequentially forming a gate insulation layer and a conductive layer on a semiconductor substrate. A buried impurity region is then formed in th... | 08/21/2007 |
| 7253058 | Method of manufacturing NOR-type mask ROM device and semiconductor device including the same A method of manufacturing a NOR-type mask ROM device includes forming a first gate electrode for an OFF cell and a second gate electrode for an ON cell on a semiconductor substrate of a first conductivity type. To code the mask ROM device, a plurality of source/drai... | 08/07/2007 |
| 7244653 | Method and structure in the manufacture of mask read only memory A method and structure of manufacture of mask ROM device is provided. Firstly, a semiconductor structure is provided that comprises a first dielectric layer, a plurality of buried bit lines and a plurality of code areas, wherein each of the code areas is placed betw... | 07/17/2007 |
| 7230877 | Method of making a semiconductor memory device A method for fabricating a semiconductor memory device is described. An insulating layer is disposed on a semiconductor substrate. A matrix of semiconductor memory elements is disposed in the substrate. The semiconductor memory elements include a plurality of contac... | 06/12/2007 |
| 7179712 | Multibit ROM cell and method therefor To increase the density of memory cells, a multibit memory cell (10, 50, 80, 110) can be manufactured by preventing the formation of at least one of the extension regions usually formed for the source or drain region. In one embodiment, a single mask (24 | 02/20/2007 |
| 7169671 | Method of recording information in nonvolatile semiconductor memory A nonvolatile semiconductor memory includes a transistor, one or two resistance-change portions, and one or two charge accumulation portions. The transistor has a control electrode, first main electrode region, and second main electrode region. Each resistance-chang... | 01/30/2007 |
| 7161216 | Depletion-mode transistor that eliminates the need to separately set the threshold voltage of the depletion-mode transistor A semiconductor circuit with a depletion-mode transistor is formed with a method that eliminates the need for a separate mask and implant step to set the threshold voltage of the depletion-mode transistor. As a result, the method of the present invention reduces the... | 01/09/2007 |
| 7157360 | Memory device and method for forming a passivation layer thereon A memory device with an improved passivation structure. The memory device includes a semiconductor substrate with memory units thereon, an interconnect structure over the surface of the semiconductor substrate to connect with the memory units, and a passivation stru... | 01/02/2007 |
| 7157336 | Method of manufacturing semiconductor device The method of manufacturing a semiconductor device comprises the steps of: forming a gate electrode on a semiconductor substrate through a gate insulated film; forming source/drain regions to be adjacent to the gate electrode forming an Al wiring through an interlay... | 01/02/2007 |
| 7135369 | Atomic layer deposited ZrAlO dielectric layers including ZrAlO An atomic layer deposited ZrAlxOy dielectric layer and a method of fabricating such a dielectric layer produce a reliable dielectric layer having an equivalent oxide thickness thinner than attainable using SiO2. Pulsing a zirconium-c... | 11/14/2006 |
| 7132334 | Methods of code programming a mask ROM device A method of code programming a mask read only memory (ROM) is disclosed. A method of the present invention includes forming a layer of developable anti-reflective coating over a plurality of code openings located on a substrate of a ROM device. The plurality of code... | 11/07/2006 |
| 7122434 | Method for generating an electrical contact with buried track conductors A semiconductor structure 300 comprises a plurality of first track conductors 303, a plurality of second track conductors 304, which are insulated with respect to the first track conductors 303 and form a grid together with these first tr... | 10/17/2006 |
| 7094649 | Method for forming multi-level mask ROM cell and NAND multi-level mask ROM The present invention relates to a multi-level read only memory cell that can store two bits and the fabrication method thereof. The multi-level ROM cell has the storage capacity of two bits and the resultant NAND type ROM memory array can provide four logic states ... | 08/22/2006 |
| 7084036 | Data writing method for mask read only memory A data writing method for mask read only memory using different doses of ion implantations to perform the data writing of Mask Read Only Memory. A semiconductor substrate having a plurality of gate structures is provided. The different ion implantations are performe... | 08/01/2006 |
| 7084463 | Semiconductor device and manufacturing method thereof A semiconductor device includes: a gate electrode on a semiconductor substrate through a gate insulated film; source/drain regions to be adjacent to said gate electrode; and an Al wiring through an interlayer insulating film covering said gate electrode, wherein imp... | 08/01/2006 |
| 7067378 | Methods of fabricating multiple sets of field effect transistors The invention includes methods of fabricating multiple sets of field effect transistors. In one implementation, an etch stop layer is formed over an insulative capping layer which is formed over a conductive gate layer formed over a substrate. The etch stop layer, t... | 06/27/2006 |
| 7064035 | Mask ROM and fabrication thereof A Mask ROM and a method for fabricating the same are described. The Mask ROM comprises a substrate, a plurality of gates on the substrate, a gate oxide layer between the gates and the substrate, a plurality of buried bit lines in the substrate between the gates, an ... | 06/20/2006 |
| 7053447 | Charge-trapping semiconductor memory device Memory cells are formed by preferably cylindrical recesses at the main surface of a semiconductor substrate, containing a memory layer sequence at sidewalls and a gate electrode and being provided with upper and lower source/drain regions connected in columns to fir... | 05/30/2006 |
