Did You Know...
...During the Civil War, the Confederacy established its own Patent Office which issued 266 patents, a third of which concerned implements of war.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8148226 | Method of fabricating semiconductor device Disclosed is a method of fabricating a semiconductor device that includes both an enhancement-mode FET and a depletion-mode FET. The method includes forming an opening in a gate electrode for the depletion-mode FET. The opening is located in or in the vicinity of on... | 04/03/2012 |
| 8110467 | Multiple Vt field-effect transistor devices Multiple threshold voltage (Vt) field-effect transistor (FET) devices and techniques for the fabrication thereof are provided. In one aspect, a FET device is provided including a source region; a drain region; at least one channel interconnecting the source and drai... | 02/07/2012 |
| 7863139 | Double gate FET and fabrication process A method of fabricating a double gate FET on a silicon substrate includes the steps of sequentially epitaxially growing a lower gate layer of crystalline rare earth silicide material on the substrate, a lower gate insulating layer of crystalline rare earth insulatin... | 01/04/2011 |
| 7425744 | Fabricating logic and memory elements using multiple gate layers Various embodiments are directed to different methods and systems relating to design and implementation of memory cells such as, for example, static random access memory (SRAM) cells. In one embodiment, a memory cell may include a first layer of conductive material ... | 09/16/2008 |
| 7339241 | FinFET structure with contacts A FinFET, which by its nature has both elevated source/drains and an elevated channel that are portions of an elevated semiconductor portion that has parallel fins and one source/drain on one side of the fins and another source/drain on the other side of the fins, h... | 03/04/2008 |
| 7276414 | NAND memory arrays and methods NAND memory arrays and methods are provided. A plurality of first gate stacks is formed on a first dielectric layer that is formed on a substrate of a NAND memory array. The first dielectric layer and the plurality of first gate stacks formed thereon form a NAND str... | 10/02/2007 |
| 7238579 | Semiconductor device for reducing photovolatic current A semiconductor device that has a common border between P and N wells is susceptible to photovoltaic current that is believed to be primarily generated from photons that strike this common border. Photons that strike the border are believed to create electron/hole p... | 07/03/2007 |
| 7230877 | Method of making a semiconductor memory device A method for fabricating a semiconductor memory device is described. An insulating layer is disposed on a semiconductor substrate. A matrix of semiconductor memory elements is disposed in the substrate. The semiconductor memory elements include a plurality of contac... | 06/12/2007 |
| 7157324 | Transistor structure having reduced transistor leakage attributes Undesirable transistor leakage in transistor structures becomes greatly reduced in substrates having a doped implant region formed via pulling back first and second layers of a process stack. A portion of the substrate, which also has first and second layers deposit... | 01/02/2007 |
| 7064034 | Technique for fabricating logic elements using multiple gate layers Various techniques are described which utilize multiple poly-silicon layers in the design and fabrication of various logic elements that are used in semiconductor devices. According to a specific implementation of the present invention, logic gate cell sizes and mem... | 06/20/2006 |
| 7002839 | Magnetic ring unit and magnetic memory device The present invention relates to a magnetic ring unit and a magnetic memory device; an object of the invention is to control the direction of rotation of the magnetic flux freely and with high reproducibility in a simple structure without using a thermal process suc... | 02/21/2006 |
| 6713354 | Coding method for mask ROM A method of manufacturing mask ROM is provided. A buried bit line is formed in a substrate and then a gate and a word line are formed over the substrate. Thereafter, a pre-coding layer with a plurality of pre-coding openings therein is formed over the substrate in a... | 03/30/2004 |
| 6713821 | Structure of a mask ROM device A mask ROM device is described. The mask ROM device includes a substrate, a gate, a double diffused source/drain region that comprises a first doped region and a second doped region, a channel region, a coding region, a dielectric layer and a word line. The gate is ... | 03/30/2004 |
| 6670247 | Method of fabricating mask read only memory A method of fabricating a mask read only memory. Embedded bit line are formed in a substrate. A gate dielectric layer and a word line are formed on the substrate. The word line is perpendicular to the bit lines. The substrate under the word line and betwe... | 12/30/2003 |
| 6667214 | Non-volatile semiconductor memory devices and methods for manufacturing the same Examples including non-volatile semiconductor memory devices in which digitized image data and voice data can be more efficiently written and read, and methods for manufacturing the same, are described. In one example, a non-volatile semiconductor memory ... | 12/23/2003 |
| 6664164 | UV-programmed P-type Mask ROM and fabrication thereof A method for fabricating an UV-programmed P-type Mask ROM is described. The threshold voltages of all memory cells are raised at first to make each memory cell be in a first logic state, in which the channel is hard to switch on, in order to prevent a lea... | 12/16/2003 |
| 6635536 | Method for manufacturing semiconductor memory device A method for manufacturing a semiconductor memory device is disclosed. A spacer of a material having a high etching selection ratio with respect to an interdielectric layer is formed on a sidewall of a gate electrode. A refractory metal silicide layer is ... | 10/21/2003 |
| 6573144 | Method for manufacturing a semiconductor device having lateral MOSFET (LDMOS) In an LDMOS, an n-type region 6, which is formed to have a concentration higher than that of an n-type substrate 1 and whose concentration gradually increases from the n-type substrate 1 to an n+ type drain region 5, is disposed so as to surrou... | 06/03/2003 |
| 6468869 | Method of fabricating mask read only memory A method of fabricating a mask read only memory. Gate stacked structures, each of which made up of a gate dielectric layer, a gate conductive layer and a gate cap layer, are formed on a substrate. Source/drain regions are between, but not adjacent to the ... | 10/22/2002 |
| 6355530 | Method of manufacturing a mask ROM bit line A method of manufacturing a mask ROM. A sacrificial silicon oxide layer is formed on the active region upon the substrate. Patterning the sacrificial silicon oxide layer in order to form a plurality of parallel openings, thereby exposing a portion of the ... | 03/12/2002 |
| 6326664 | Transistor with ultra shallow tip and method of fabrication A novel transistor with a low resistance ultra shallow tip region and its method of fabrication. The novel transistor of the present invention has a source/drain extension or tip comprising an ultra shallow region which extends beneath the gate electrode ... | 12/04/2001 |
| 6274896 | Drive transistor with fold gate A drive transistor for an ink jet print head includes a semiconductor substrate having a serpentine channel of a first type doping, the channel comprising substantially parallel first and second serpentine channel portions, the first and second serpentine... | 08/14/2001 |
| 6258672 | Method of fabricating an ESD protection device An ESD protection structure that when connected between an input/output pad on a semiconductor substrate and a reference voltage source, will protect internal circuits formed on the semiconductor substrate from over stress due to excessively high voltages... | 07/10/2001 |
| 6200843 | High-voltage, high performance FETs A method for forming a semiconductor device. A substrate is provided. A first electrically insulating layer is formed on the substrate. A second electrically insulating layer is formed on the first electrically insulating layer. Openings are formed throug... | 03/13/2001 |
| 6190974 | Method of fabricating a mask ROM A method of fabricating a mask read-only memory. Before carrying out a code implantation, a coding mask is used as an etching mask to remove a portion of the inter-metal dielectric layer and the inter-layer dielectric layer above the coding positions, the... | 02/20/2001 |
| 6093604 | Method of manufacturing a flash memory device A memory device and a method of manufacturing the same in accordance with the present invention has an improved writing and erasing efficiency and an improved reliability. The memory device includes a first conductivity type substrate having second conduc... | 07/25/2000 |
| 5976937 | Transistor having ultrashallow source and drain junctions with reduced gate overlap and method Method of making transistors having ultrashallow source and drain junction with reduced gate overlap may comprise forming a first gate electrode (124) separated from a first active area (126) of a semiconductor layer (112) by a first gate insulator (130).... | 11/02/1999 |
| 5963800 | CMOS integration process having vertical channel The present invention relates to processes for fabrictation of Vertical MISFET devices or a stack of several Vertical MISFET devices having high fabrication yield.... | 10/05/1999 |
| 5950089 | Method of making read-only memory device having a silicon-on-insulator structure A semiconductor read-only memory (ROM) device having a silicon-on-insulator (SOI) structure and a method for fabricating the same are provided. The SOI structure permits isolation of the source/drain regions from the underlying substrate, thereby preventi... | 09/07/1999 |
| 5933735 | Semiconductor read-only memory device and method of fabricating the same A ROM (read-only memory) device of the type including an array of MOSFET (metal-oxide semiconductor field-effect transistor) memory cells and a method for fabricating the same are provided. The method allows for better planarization of the wafer surface o... | 08/03/1999 |
| 5866458 | Method for fabricating a CMOS A CMOS fabrication method includes the steps of providing a substrate having a surface, forming a first conductive well adjacent to the surface of the substrate, forming a second conductive well adjacent to the surface of the substrate, a portion of the f... | 02/02/1999 |
| 5856216 | Method of manufacturing a semiconductor integrated circuit device including an SRAM A semiconductor integrated circuit device includes a first conductor formed on a main surface of a semiconductor substrate with an insulating film therebetween, and a second conductor formed with an insulating film therebetween so as to be placed near one... | 01/05/1999 |
| 5854109 | Silicide process for manufacturing a mask ROM A self-aligned silicide process for the formation of a mask ROM includes forming a self-aligned silicide layer over the bit lines and the word lines to lower the resistance of the bit lines and word lines in the mask ROM.... | 12/29/1998 |
| 5846863 | Method for manufacturing a semiconductor ROM device A semiconductor memory device and a method for manufacturing the same are disclosed. The device includes a plurality of active regions repeatedly formed extending in parallel to each other, a device isolation region, a plurality of first gate electrodes r... | 12/08/1998 |
| 5811322 | Method of making a broadband backside illuminated MESFET with collecting microlens A composite-layer semiconductor device includes a gate above a host substrate, an n++ contact layer above the gate, and source and drain ohmic contacts applied to the n++ contact layer. The source and drain ohmic contacts define a central gate location wh... | 09/22/1998 |
| 5792697 | Method for fabricating a multi-stage ROM A method of forming a multi-stage ROM which replaces the multiple code implant. A gate oxide layer, a first polysilicon layer, an oxide layer, a second polysilicon layer and a silicon nitride layer are formed over a substrate in succession. Then, the sili... | 08/11/1998 |
| 5786253 | Method of making a multi-level ROM device A method of making multi-level ROM devices in which the gate width controls the threshold voltage setting of each memory unit, instead of the conventional method of setting the threshold voltage through the implantation of ions into the channel region of ... | 07/28/1998 |
| 5744392 | Process for fabricating a multi-stage read-only memory device A multi-stage ROM device capable of storing multi-stage data and allowing high packing density for a ROM chip thus fabricated and a process for fabricating such a multi-stage ROM device. In the ROM device, the intersection between a first bit line and a w... | 04/28/1998 |
| 5264386 | Read only memory manufacturing method A method for making a Read Only Memory having spaced source and drain regions in a substrate and a plurality of closely spaced gate electrodes on the surface, spanning the distance between the source and drain. The method features the fabrication of a dou... | 11/23/1993 |
| 5149664 | Self-aligning ion-implantation method for semiconductor device having multi-gate type MOS transistor structure A self-aligning ion-implantation method for forming multi-gate MOS transistor structures within a semiconductor cell array on a substrate is provided. Each structure includes a plurality of first gate electrode layers and a plurality of second gate electr... | 09/22/1992 |
