Class 438/276 - Introducing a dopant into the channel region of selected transistors

Subclass of Class 438 - Semiconductor device manufacturing: process
Definition: Process for making plural insulated gate field effect transistors
No. of patents: 372
Last issue date: 05/15/2012

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Number	Title	Issue Date
8178410	Method for fabricating a semiconductor power device A method for forming a power device includes the following steps. An epitaxial layer is formed on a substrate. A pad layer and hard mask are formed on the epitaxial layer. A trench is etched into the hard mask, the pad layer, and the epitaxial layer. The hard mask i...	05/15/2012
8084328	Semiconductor device including I/O oxide nitrided core oxide on substrate A semiconductor device includes a semiconductor substrate, wherein the semiconductor substrate includes a core area for core circuits and a peripheral area for peripheral circuits. The semiconductor device includes a core oxide on the semiconductor substrate in the ...	12/27/2011
8071451	Method of doping semiconductors A method of doping a semiconductor body is provided herein. In one embodiment, a semiconductor body is exposed to an activated hydrogen gas for a predetermined time period and temperature. The activated hydrogen gas that is configured to react with a surface of a se...	12/06/2011
7955931	Method and apparatus for fabricating a carbon nanotube transistor A method of fabricating a nanotube field-effect transistor having unipolar characteristics and a small inverse sub-threshold slope includes forming a local gate electrode beneath the nanotube between drain and source electrodes of the transistor and doping portions ...	06/07/2011
7932153	Semiconductor device and method for fabricating the same A threshold control layer of a second MIS transistor is formed under the same conditions for forming a threshold control layer of a first MIS transistor. LLD regions of the second MIS transistor are formed under the same conditions for forming LDD regions of a third...	04/26/2011
7888213	Conductive channel pseudo block process and circuit to inhibit reverse engineering A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed by a plurality of layers of material having a controlled outline. A layer of conductive material having a controlled outline is disposed among...	02/15/2011
7863138	Methods of forming nano line structures in microelectronic devices A method of forming a microelectronic device includes forming a groove structure having opposing sidewalls and a surface therebetween on a substrate to define a nano line arrangement region. The nano line arrangement region has a predetermined width and a predetermi...	01/04/2011
7824988	Method of forming an integrated circuit A method includes forming a source, a drain, and a disposable gate (38) of the first transistor; forming a source, a drain, and a disposable gate of the second transistor; removing the disposable gates of the first transistor and the second transistor; formin...	11/02/2010
7763516	Manufacturing method of semiconductor device having trench isolation A manufacturing method of semiconductor device includes: forming a nitride film above a silicon substrate including a first region and a second region which respectively correspond to an outside of a memory cell region and the memory cell region; forming trenches re...	07/27/2010
7754569	Anti-halo compensation An apparatus and method for controlling the net doping in the active region of a semiconductor device in accordance with a gate length is provided. A compensating dopant is chosen to be a type of dopant which will electrically neutralize dopant of the opposite type ...	07/13/2010
7687353	Ion implantation method for high voltage device A method of performing ion implantation method for a high-voltage device. The method includes defining a logic region and a high-voltage region in a semiconductor substrate, forming a first gate insulation layer on the semiconductor substrate in the logic region and...	03/30/2010
7682910	Method of selectively adjusting ion implantation dose on semiconductor devices A first semiconductor region and a second semiconductor region separated by a shallow trench isolation region are formed in a semiconductor substrate. A photoresist is applied and patterned so that the first semiconductor region is exposed, while the second semicond...	03/23/2010
7662689	Strained transistor integration for CMOS Various embodiments of the invention relate to a CMOS device having (1) an NMOS channel of silicon material selectively deposited on a first area of a graded silicon germanium substrate such that the selectively deposited silicon material experiences a tensile strai...	02/16/2010
7645672	Mask ROM, method for fabricating the same, and method for coding the same A mask ROM, a method for fabricating the same and a method for coding the same are disclosed. The method for forming the mask ROM maximizes packing density and integration of a device. The mask ROM includes a semiconductor substrate having a device isolation region ...	01/12/2010
7615453	Method of manufacturing a semiconductor integrated circuit device In the chip with which a plurality of MISFET from which threshold value voltage differs is intermingled, leakage current, such as GIDL current and BTBT current, is suppressed, inhibiting the short channel effect of MISFET. The concentration of the impurity for thres...	11/10/2009
7595243	Fabrication of semiconductor structure having N-channel channel-junction field-effect transistor A semiconductor technology combines a normally off n-channel channel-junction insulated-gate field-effect transistor (“IGFET”) (104) and an n-channel surface-channel IGFET (100 or 160) to reduce low-frequency 1/f noise. The channel-junction ...	09/29/2009
7488652	Manufacturing method of gate oxidation films After forming a field insulating film 12 on a substrate, sacrificing or gate oxidation films are formed as oxidation films 14a and 14b. An ion implantation layer 18 is formed by one or plurality of implantation process of ar...	02/10/2009
7488653	Semiconductor device and method for implantation of doping agents in a channel A semiconductor device includes a substrate of a first type of conductivity provided with at least one gate on one of its faces, and at least two doped regions of a second type of conductivity for forming a drain region and a source region. The two doped regions are...	02/10/2009
7482233	Embedded non-volatile memory cell with charge-trapping sidewall spacers An IC includes both “volatile” CMOS transistors (FETs) and embedded non-volatile memory (NVM) cells, both including polysilicon gate structures, sidewall oxide layers, sidewall spacer structures, and source/drain regions. The sidewall spacers of both the NVM cel...	01/27/2009
7482232	Method for fabricating a nanotube field effect transistor The method includes forming a 1-10000 nm thick SiO2, HfO2, Al2O3 and/or quartz gate dielectric on an Si back gate. An Al or Mo gate electrode is formed on the gate dielectric. An Al2O3 insulating laye...	01/27/2009
7439140	Formation of standard voltage threshold and low voltage threshold MOSFET devices Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within...	10/21/2008
7432164	Semiconductor device comprising a transistor having a counter-doped channel region and method for forming the same A method for making a semiconductor device includes providing a first substrate region and a second substrate region, wherein at least a part of the first substrate region has a first conductivity type and at least a part of the second substrate region has a second ...	10/07/2008
7413946	Formation of standard voltage threshold and low voltage threshold MOSFET devices Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within...	08/19/2008
7405129	Device comprising doped nano-component and method of forming the device A device comprising a doped semiconductor nano-component and a method of forming the device are disclosed. The nano-component is one of a nanotube, nanowire or a nanocrystal film, which may be doped by exposure to an organic amine-containing dopant. Illustrative exa...	07/29/2008
7402495	Method for manufacturing a semiconductor device A method of manufacturing a semiconductor device includes forming a first semiconductor region of a first conductive type and a second semiconductor region of a second conductive type in a predetermined region of the semiconductor substrate of a first conductive typ...	07/22/2008
7399678	Method for reading an array of multi-bit ROM cells with each cell having bi-directional read A array of multi-bit Read Only Memory (ROM) cells is in a semiconductor substrate of a first conductivity type with a first concentration. Each ROM cell has a first and second regions of a second conductivity type spaced apart from one another in the substrate. A ch...	07/15/2008
7396727	Transistor of semiconductor device and method for fabricating the same A transistor which may effectively control the short channel effect with a vertical transistor structure. This structure may prevent the degradation of a transistor's performance caused by the hot carrier effect. The transistor has a source region having a concentra...	07/08/2008
7385232	CMOS imager with enhanced transfer of charge and low voltage operation and method of formation A dopant gradient region of a first conductivity type and a corresponding channel impurity gradient below a transfer gate and adjacent a charge collection region of a CMOS imager photodiode are disclosed. The channel impurity gradient in the transfer gate provides a...	06/10/2008
7354825	Methods and apparatus to form gates in semiconductor devices A method of formation a gate in a semiconductor device includes forming a gate oxide layer and a sacrificial layer on a semiconductor substrate. The sacrificial layer is then selectively etched to form a sidewall opening. Next, a polycrystalline silicon layer is for...	04/08/2008
7354817	Semiconductor device, manufacturing method thereof, and CMOS integrated circuit device A semiconductor device includes a semiconductor substrate. A gate electrode is formed on the semiconductor substrate via a gate insulating film. A source region and a drain region of a first conductivity type are formed on the first side and the second side of the g...	04/08/2008
7352047	Systems and methods for integration of heterogeneous circuit devices A heterogeneous device comprises a substrate and a plurality of heterogeneous circuit devices defined in the substrate. In embodiments, a plurality of heterogeneous circuit devices are integrated by successively masking and ion implanting the substrate. The heteroge...	04/01/2008
7352035	Flash memory devices and methods for fabricating flash memory devices A flash memory device includes a cell string having a plurality of cell transistors connected in series, and a string selection transistor and a ground selection transistor connected to both ends of the cell string, respectively, wherein the cell transistor has a ch...	04/01/2008
7342276	Method and apparatus utilizing monocrystalline insulator A semiconductor device, including: a semiconductor material; a conductive element; and a substantially monocrystalline insulator disposed between the semiconductor material and the conductive eleme...	03/11/2008
7341930	Systems and methods for integration of heterogeneous circuit devices A heterogeneous device comprises a substrate and a plurality of heterogeneous circuit devices defined in the substrate. In embodiments, a plurality of heterogeneous circuit devices are integrated by successively masking and ion implanting the substrate. The heteroge...	03/11/2008
7335918	Silicon nitride film and semiconductor device, and manufacturing method thereof An object of the present invention is to apply an insulating film of cure and high quality that is suitably applicable as gate insulating film and protective film to a technique that the insulating film is formed on the glass substrate under a temperature of strain ...	02/26/2008
7329569	Methods of forming semiconductor devices including mesa structures and multiple passivation layers A method of forming a semiconductor device may include forming a semiconductor structure on a substrate wherein the semiconductor structure defines a mesa having a mesa surface opposite the substrate and mesa sidewalls between the mesa surface and the substrate. A f...	02/12/2008
7326995	Trench MIS device having implanted drain-drift region and thick bottom oxide A trench MIS device is formed in a P-epitaxial layer that overlies an N+ substrate. In one embodiment, the device includes a thick oxide layer at the bottom of the trench and an N-type drain-drift region that extends from the bottom of the trench to the substrate. T...	02/05/2008
7323420	Method for manufacturing multi-thickness gate dielectric layer of semiconductor device In a method for manufacturing a multi-thickness gate dielectric layer of a semiconductor device, a first dielectric layer is formed on a semiconductor substrate. A second dielectric layer is formed using a different dielectric material from the material constituting...	01/29/2008
7314794	Low-cost high-performance planar back-gate CMOS A method of fabricating a high-performance planar back-gate CMOS structure having superior short-channel characteristics and reduced capacitance using processing steps that are not too lengthy or costly is provided. Also provided is a high-performance planar back-ga...	01/01/2008
7314800	Application of different isolation schemes for logic and embedded memory The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relat...	01/01/2008

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Class 438/276 - Introducing a dopant into the channel region of selected transistors