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Behavior Modification Wristwatch
A wristwatch including a watch band and a watch body having an octagon shaped perimeter and being red in color and having the word STOP thereon to resemble a stop sign.
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| Number | Title | Issue Date |
| 8187942 | Method for manufacturing semiconductor device having a dual gate insulation layer A method for manufacturing a semiconductor device having a dual gate insulation layer is presented. The method includes a step of forming a first insulation layer on a semiconductor substrate which has a first region and a second region. The method includes a step o... | 05/29/2012 |
| 8183115 | Method of manufacturing a semiconductor device having elevated layers of differing thickness There is provided an SOI-MISFET including: an SOI layer; a gate electrode provided on the SOI layer interposing a gate insulator; and a first elevated layer provided higher in height from the SOI layer than the gate electrode at both sidewall sides of the gate elect... | 05/22/2012 |
| 8183114 | Semiconductor device and manufacturing method thereof for reducing the area of the memory cell region A structure is adopted for a layout of an SRAM cell which provides a local wiring 3a between a gate 2a and gate 2b and connects an active region 1a and an active region 1b. This eliminates the nec... | 05/22/2012 |
| 8168499 | Semiconductor device and method for manufacturing the same It is made possible to provide a method for manufacturing a semiconductor device that includes CMISs each having a low threshold voltage Vth and a Ni-FUSI/SiON or high-k gate insulating film structure. The method comprises: forming a p-type semiconductor region and ... | 05/01/2012 |
| 8158481 | CMOS structure and method for fabrication thereof using multiple crystallographic orientations and gate materials Methods for fabricating a CMOS structure use a first gate stack located over a first orientation region of a semiconductor substrate. A second gate material layer is located over the first gate stack and a laterally adjacent second orientation region of the semicond... | 04/17/2012 |
| 8148225 | Fully-depleted (FD)(SOI) MOSFET access transistor and method of fabrication A fully-depleted (FD) Silicon-on-Insulator (SOI) MOSFET access transistor comprising a gate electrode of a conductivity type which is opposite the conductivity type of the source/drain regions and a method of fabrication are disclosed. ... | 04/03/2012 |
| 8133787 | SiC semiconductor device and method for manufacturing the same A SiC semiconductor device having a MOS structure includes: a SiC substrate; a channel region providing a current path; first and second impurity regions on upstream and downstream sides of the current path, respectively; and a gate on the channel region through the... | 03/13/2012 |
| 8114744 | Methods for reducing gate dielectric thinning on trench isolation edges and integrated circuits therefrom A method of fabricating an integrated circuit (IC) including a plurality of MOS transistors and ICs therefrom include providing a substrate having a silicon including surface, and forming a plurality of dielectric filled trench isolation regions in the substrate, wh... | 02/14/2012 |
| 8101485 | Replacement gates to enhance transistor strain Some embodiments of the present invention include apparatuses and methods relating to NMOS and PMOS transistor strain. ... | 01/24/2012 |
| 8088663 | SRAM cell having a rectangular combined active area planar pass gate and planar pull-down NFETS A planar pass gate NFET is designed with the same width as a planar pull-down NFET. To optimize a beta ratio between the planar pull-down NFET and an adjoined planar pass gate NFET, the threshold voltage of the planar pass gate NFET is increased by providing a diffe... | 01/03/2012 |
| 8053317 | Method and structure for improving uniformity of passive devices in metal gate technology Method of forming a semiconductor device which includes the steps of obtaining a semiconductor substrate having a logic region and an STI region; sequentially depositing layers of high K material, metal gate, first silicon and hardmask; removing the hardmask and fir... | 11/08/2011 |
| 8048744 | Semiconductor device and fabricating method thereof A semiconductor device and fabricating method thereof are disclosed. The method includes forming a polysilicon layer on a semiconductor substrate including a high-voltage area and a low-voltage area, partially etching the polysilicon layer in the low-voltage area, f... | 11/01/2011 |
| 8043916 | Method of fabricating semiconductor device having multiple gate insulating layer A method of fabricating a semiconductor device is provided. The method includes preparing a semiconductor substrate having first and second regions, forming a mask layer pattern on the second region, growing an oxidation retarding layer on the first region and remov... | 10/25/2011 |
| 8039349 | Methods for fabricating non-planar semiconductor devices having stress memory Embodiments of a method are provided for fabricating a non-planar semiconductor device including a substrate having a plurality of raised crystalline structures formed thereon. In one embodiment, the method includes the steps of amorphorizing a portion of each raise... | 10/18/2011 |
| 8034687 | Methods of forming a plurality of transistor gates, and methods of forming a plurality of transistor gates having at least two different work functions A method of forming a plurality of transistor gates having at least two different work functions includes forming first and second transistor gates over a substrate having different widths, with the first width being narrower than the second width. A material is dep... | 10/11/2011 |
| 8012835 | Method of high voltage operation of field effect transistor A high voltage operating field effect transistor has a source region and a drain region spaced apart from each other in a surface of a substrate. The source region is operative to receive at least one of a signal electric potential and a signal current. A semiconduc... | 09/06/2011 |
| 7994009 | Low cost transistors using gate orientation and optimized implants An integrated circuit is disclosed having symmetric and asymmetric MOS transistors of the same polarity, oriented perpendicularly to each other, formed by concurrent halo ion, LDD ion and/or S/D ion implant processes using angled, rotated sub-implants which vary the... | 08/09/2011 |
| 7985652 | Metal stress memorization technology A semiconductor device and method for manufacturing a tensile strained NMOS and a compressive strained PMOS transistor pair, wherein a stressor material is sacrificial is disclosed. The method provides for a substrate, which includes a source/drain for an NMOS trans... | 07/26/2011 |
| 7977194 | Method for fabricating semiconductor device with fully silicided gate electrode A method for fabricating a semiconductor device includes the steps of: forming a first MISFET including first source/drain regions and a first gate electrode of a polycrystalline silicon, and a second MISFET including second source/drain regions and a second gate el... | 07/12/2011 |
| 7972929 | Method for manufacturing semicondcutor device A method for manufacturing a semiconductor device includes forming an ONO layer in a memory region and forming several gate oxide layer patterns in a logic region, a nitride layer in the logic region can be used as a hard mask, enabling a reduction in the number of ... | 07/05/2011 |
| 7951678 | Metal-gate high-k reference structure Disclosed are embodiments of an integrated circuit structure that incorporates at least two field effect transistors (FETs) that have the same conductivity type and essentially identical semiconductor bodies (i.e., the same semiconductor material and, thereby the sa... | 05/31/2011 |
| 7932152 | Method of forming a gate stack structure A method of forming an integrated circuit structure on a substrate, the substrate includes a primary region and a secondary region. A first layer of a first material of a first thickness is formed over the substrate. A portion of the first layer is removed over the ... | 04/26/2011 |
| 7910444 | Process for forming differential spaces in electronics device integrated on a semiconductor substrate A forms spacers in a electronic device integrated on a semiconductor substrate that includes: first and second transistors each comprising a gate electrode projecting from the substrate and respective source/drain regions. The process comprises: forming in cascade a... | 03/22/2011 |
| 7910441 | Multi-gate semiconductor device and method for forming the same A semiconductor device includes a substrate (20), a source region (58) formed over the substrate, a drain region (62) formed over the substrate, a first gate electrode (36) over the substrate adjacent to the source region and between the ... | 03/22/2011 |
| 7910443 | Method involving trimming a hard mask in the peripheral region of a semiconductor device A method for fabricating a semiconductor device includes forming a conductive material layer for forming a gate over a substrate including a cell region and a peripheral region, forming hard mask patterns over the conductive material layer, forming a mask pattern ov... | 03/22/2011 |
| 7910442 | Process for making a semiconductor device using partial etching A method including partially etching a first portion of a first layer, wherein the first layer is a conductive layer, is provided. The method further includes removing at least a portion of a second layer. The method further includes completing etching of said first... | 03/22/2011 |
| 7897466 | Method for manufacturing semiconductor device There is provided a method for manufacturing a semiconductor device having a high breakdown voltage transistor and a low breakdown voltage transistor provided on a same semiconductor substrate. The method includes forming a first gate electrode of the high breakdown... | 03/01/2011 |
| 7897467 | Semiconductor integrated circuit device and manufacturing method thereof After silicon oxide film (9) is formed on the surface of a semiconductor substrate (1), the silicon oxide film (9) in a region in which a gate insulation film having a small effective thickness is formed is removed using diluted HF and after tha... | 03/01/2011 |
| 7883971 | Gate structure in a trench region of a semiconductor device and method for manufacturing the same Disclosed are a gate structure in a trench region of a semiconductor device and a method for manufacturing the same. The semiconductor device includes a pair of drift regions formed in a semiconductor substrate; a trench region formed between the pair of drift regio... | 02/08/2011 |
| 7875516 | Integrated circuit including a first gate stack and a second gate stack and a method of manufacturing An integrated circuit including a first gate stack and a second gate stack and a method of manufacturing is disclosed. One embodiment provides non-volatile memory cells including a first gate stack and a gate dielectric on a first surface section of a main surface o... | 01/25/2011 |
| 7867858 | Hybrid transistor based power gating switch circuit and method A method includes forming a first transistor having a first gate dielectric thickness and a first source/drain extension depth, a second transistor having a second gate dielectric thickness and the first source/drain extension depth, and a third transistor having th... | 01/11/2011 |
| 7858479 | Method and apparatus of fabricating semiconductor device An object is to provide a semiconductor device in which uniform properties are intended and high yields are provided. Process steps are provided in which variations are adjusted in doping and annealing process steps that are subsequent process steps so as to cancel ... | 12/28/2010 |
| 7855116 | Nonvolatile semiconductor memory device and manufacturing method thereof In a nonvolatile semiconductor memory device which has a nonvolatile memory cell portion, a low-voltage operating circuit portion of a peripheral circuit region and a high-voltage operating circuit portion of the peripheral circuit region formed on a substrate and i... | 12/21/2010 |
| 7846800 | Avoiding plasma charging in integrated circuits A circuit having a circuit control terminal, a primary circuit and a protection circuit is provided. The primary circuit includes a primary control terminal and a primary gate oxide of a thickness T1. The primary control terminal is coupled to the circuit... | 12/07/2010 |
| 7838366 | Method for fabricating a metal gate structure A method of fabricating a metal gate structure is provided. The method includes providing a semiconductor substrate with a planarized polysilicon material; patterned the planarized polysilicon material to form at least a first gate and a second gate, wherein the fir... | 11/23/2010 |
| 7824987 | Method of manufacturing a semiconductor device including a SRAM section and a logic circuit section A semiconductor device including a SRAM section and a logic circuit section includes: a first n-type MIS transistor including a first n-type gate electrode formed with a first gate insulating film interposed on a first element formation region of a semiconductor sub... | 11/02/2010 |
| 7824986 | Methods of forming a plurality of transistor gates, and methods of forming a plurality of transistor gates having at least two different work functions A method of forming a plurality of transistor gates having at least two different work functions includes forming first and second transistor gates over a substrate having different widths, with the first width being narrower than the second width. A material is dep... | 11/02/2010 |
| 7820512 | Spacer patterned augmentation of tri-gate transistor gate length In general, in one aspect, a method includes forming a semiconductor substrate having N-diffusion and P-diffusion regions. A gate stack is formed over the semiconductor substrate. A gate electrode hard mask is formed over the gate stack. The gate electrode hard mask... | 10/26/2010 |
| 7816211 | Method of making a semiconductor device having high voltage transistors, non-volatile memory transistors, and logic transistors A semiconductor device is made on a semiconductor substrate. A first insulating layer is formed on the semiconductor substrate for use as a gate dielectric for a high voltage transistor in a first region of the semiconductor substrate. After the first insulating lay... | 10/19/2010 |
| 7807537 | Method for forming silicon oxide film and for manufacturing capacitor and semiconductor device After forming a silicon nitride film 14 on a silicon oxide film 12 covering one main surface of a semiconductor substrate 10 by a CVD method, argon ions Ar+ are doped to a part (where oxidation speed should be reduced) of the silicon ... | 10/05/2010 |
