Did You Know...
...that in 1800 ether was first used by partyers as a fun diversion? Sniffing the gas led to hilarious and raucous laughter as people watched each other become more and more intoxicated and silly. Several doctors independently realized the value ether would have to anesthetize surgery patients. Of those who claimed rights to the "discovery," none had a happy ending. One had a seizure and died defending his rights. Another spent his life in an asylum because he had been denied acclaim. A third became addicted to chloroform and, in a New York City jail, he soaked a cloth in the drug, severed an artery and bled to death.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7651918 | Strained semiconductor power device and method Semiconductor structures (52-9, 52-11, 52-12) and methods (100-300) are provided for a semiconductor devices employing strained (70) and relaxed (66) semiconductors, The method comprises, forming (106, 208, ... | 01/26/2010 |
| 7510938 | Semiconductor superjunction structure Semiconductor structures and methods are provided for a semiconductor device (54-11, 54-12) employing a superjunction structure (81). The method comprises, forming (52-6) first spaced-apart regions (70-1, 70- | 03/31/2009 |
| 7372105 | Semiconductor device with power supply impurity region A semiconductor device in which by fixing a well at a predetermined potential via a contact within a memory cell, latch-up immunity is improved without accompanying increase in the area of the memory cell, and of which manufacture is facilitated, and a manufacturing... | 05/13/2008 |
| 7358141 | Semiconductor device and method for fabricating the same Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of ... | 04/15/2008 |
| 7332750 | Power semiconductor device with improved unclamped inductive switching capability and process for forming same A power semiconductor device having high avalanche capability comprises an N+ doped substrate and, in sequence, N− doped, P− doped, and P+ doped semiconductor layers, the P− and P+ doped layers ... | 02/19/2008 |
| 7135420 | Semiconductor device and manufacturing method thereof Single crystal silicon is grown in a [100] direction to make a bulk. Next, a silicon substrate with a normal of a surface extending in an inclined direction from a [100] direction is cut from the bulk. At this time, when an angle (off-angle) of inclination of the no... | 11/14/2006 |
| 7084034 | High voltage MOS-gated power device and related manufacturing process MOS-gated power device including a plurality of elementary functional units, each elementary functional unit including a body region of a first conductivity type formed in a semiconductor material layer of a second conductivity type. A plurality of doped regions of ... | 08/01/2006 |
| 7071537 | Power device having electrodes on a top surface thereof A power device includes a substrate assembly including an upper surface and a lower surface. The substrate assembly includes a first layer and a second layer. The first layer overlies the second layer and has different conductivity than the second layer. A first ele... | 07/04/2006 |
| 7045845 | Self-aligned vertical gate semiconductor device A transistor (10) is formed in a semiconductor substrate (12) whose top surface (48) is formed with a pedestal structure (24). A conductive material (40) is disposed along a side surface (28) of the pedestal structure to sel... | 05/16/2006 |
| 7005352 | Trench-type MOSFET having a reduced device pitch and on-resistance A trench-type lateral power MOSFET is manufactured by forming an n−-type diffusion region, which will be a drift region, on a p−-type substrate; selectively removing a part of substrate and a part of n−-type diffusion region to... | 02/28/2006 |
| 6979863 | Silicon carbide MOSFETs with integrated antiparallel junction barrier Schottky free wheeling diodes and methods of fabricating the same Silicon carbide semiconductor devices and methods of fabricating silicon carbide semiconductor devices have a silicon carbide DMOSFET and an integral silicon carbide Schottky diode configured to at least partially bypass a built in diode of the DMOSFET. The Schottky... | 12/27/2005 |
| 6979621 | Trench MOSFET having low gate charge A trench MOSFET device comprising: (a) a silicon substrate of a first conductivity type (preferably N-type conductivity); (b) a silicon epitaxial layer of the first conductivity type over the substrate, the epitaxial layer having a lower majority carrier concentrati... | 12/27/2005 |
| 6977203 | Method of forming narrow trenches in semiconductor substrates A method of forming a trench within a semiconductor substrate. The method comprises, for example, the following: (a) providing a semiconductor substrate; (b) providing a patterned first CVD-deposited masking material layer having a first aperture over the semiconduc... | 12/20/2005 |
| 6939776 | Semiconductor device and a method of fabricating the same A power MOSFET comprises: a semiconductor substrate 21 of a first conduction type; a drain layer 22 of the first conduction type and formed on a surface layer of the substrate; a gate insulating film 25 formed in a partial region on the drain la... | 09/06/2005 |
| 6921938 | Double diffused field effect transistor having reduced on-resistance A double diffused field effect transistor and a method of forming the same is provided. The method begins by providing a substrate of a first conductivity type. Next, at least one dopant species, also of the first conductivity type, is introduced into a surface of t... | 07/26/2005 |
| 6921697 | Method for making trench MIS device with reduced gate-to-drain capacitance Trench MIS devices including a thick insulative layer at the bottom of the trench are disclosed, along with methods of fabricating such devices. An exemplary trench MOSFET embodiment includes a thick oxide layer at the bottom of the trench, with no appreciable chang... | 07/26/2005 |
| 6905916 | Method for processing a surface of an SiC semiconductor layer and Schottky contact A method for treating a surface on an SiC semiconductor body produced by epitaxy. According to the method, the parts of the epitactic layer that are deposited in the final phase of the epitaxy are removed by etching and a wet chemical treatment is then carried out i... | 06/14/2005 |
| 6897525 | Semiconductor device and method of manufacturing the same In order to improve the characteristics of the high breakdown voltage MOS, a semiconductor device of the present invention is characterized in that an LDMOS transistor, which comprises a source region 4, a channel region 8, and a drain region 5,... | 05/24/2005 |
| 6875657 | Method of fabricating trench MIS device with graduated gate oxide layer A process for manufacturing a trench MIS device includes depositing a conformal nitride layer in the trench; etching the nitride layer to create an exposed area at the bottom of the trench; and heating the substrate and thereby growing an oxide layer in the exposed ... | 04/05/2005 |
| 6855581 | Method for fabricating a high-voltage high-power integrated circuit device The present invention relates to a method of fabricating a high-voltage high-power integrated circuit device using a substrate of a SOI structure in which an insulating film and a silicon layer are sequentially stacked on a silicon substrate. The method comprising t... | 02/15/2005 |
| 6787420 | Semiconductor device with alternating conductivity type layer and method of manufacturing the same This invention clarifies the effects of parameters and enables the mass production of a super-junction semiconductor device, which has a drift layer composed of a parallel pn layer that conducts electricity in the ON state and is depleted in the OFF state. The quant... | 09/07/2004 |
| 6781163 | Heterojunction field effect transistor A region of an Si layer (15) located between source and drain regions (19 and 20) is an Si body region (21) which contains an n-type impurity of high concentration. An Si layer (16) and an SiGe layer (17) are, in an as grown... | 08/24/2004 |
| 6768167 | MIS semiconductor device and the manufacturing method thereof A MIS semiconductor device has a greatly improved relation between the on-resistance and the switching time by forming trench completely through a p base region and positioning the trench adjacent to a gate electrode, and then implanting n-type impurity ions using t... | 07/27/2004 |
| 6762080 | Method of manufacturing a semiconductor device having a cathode and an anode from a wafer In a method of manufacturing a semiconductor element (6) having a cathode (3) and an anode (5), the starting material used is a relatively thick wafer (1) to which, as a first step, a barrier region (21) is added on the anode side.... | 07/13/2004 |
| 6756259 | Gate insulating structure for power devices, and related manufacturing process Semiconductor power device including a semiconductor layer of a first type of conductivity, wherein a body region of a second type of conductivity including source regions of the first type of conductivity is formed, a gate oxide layer superimposed to the semiconduc... | 06/29/2004 |
| 6638824 | Metal gate double diffusion MOSFET with improved switching speed and reduced gate tunnel leakage A double-diffused metal-oxide-semiconductor ("DMOS") field-effect transistor (10) with a metal gate (26). A sacrificial gate layer is patterned to provide a self-aligned source mask. The source regions (20) are thus aligned to the gate (26), and the sourc... | 10/28/2003 |
| 6639275 | Semiconductor device with vertical MOSFET A semiconductor device improves the gate withstand voltage of vertical MOSFETs and raises their operation speed. The gate electrode is formed in the trench of the second semiconductor layer. The interlayer dielectric layer has the contact hole that expose... | 10/28/2003 |
| 6589337 | Method of producing silicon carbide device by cleaning silicon carbide substrate with oxygen gas In a process of producing a SiC device, a Si layer is formed on the surface of a SiC substrate, and the Si layer is removed from the surface of the SiC substrate by supplying oxygen gas to the Si layer in a high ambient temperature and a low ambient press... | 07/08/2003 |
| 6524894 | Semiconductor device for use in power-switching device and method of manufacturing the same An N+ buffer layer formed on the underside of an N- layer includes an inactive region having incompletely activated ions and an active region having highly activated ions. The carrier concentration of the active region is higher than... | 02/25/2003 |
| 6468866 | Single feature size MOS technology power device A MOS technology power device comprises a semiconductor material layer of a first conductivity type, a conductive insulated gate layer covering the semiconductor material layer, and a plurality of elementary functional units. The conductive insulated gate... | 10/22/2002 |
| 6432775 | Trench DMOS transistor structure having a low resistance path to a drain contact located on an upper surface A semiconductor device includes a first region of semiconductor material, which is doped to a first concentration with a dopant of a first conductivity type. A gate trench formed within the first region has sides and a bottom. A drain access trench is als... | 08/13/2002 |
| 6376311 | Vertical double diffused MOSFET and method for manufacturing same A vertical double diffuses MOSFET includes a nitride film (26) formed on a gate electrode (18). An ion implant window (34) is formed through the nitride film. P-type ions are implanted through the ion implant window into the semiconductor substrate (12), ... | 04/23/2002 |
| 6319778 | Method of making light emitting diode A method of making a light emitting diode (LED) is disclosed. An emitting light absorbed by a substrate can be prevented by using a metal with high conductivity and high reflectivity and a bonding process can be produced at a lower temperature and a bette... | 11/20/2001 |
| 6294431 | Process of manufacture of a non-volatile memory with electric continuity of the common source lines A process for the manufacture of a non-volatile memory with memory cells arranged in word lines and columns in a matrix structure, with source lines extending parallel and intercalate to said lines, said source lines formed by active regions intercalated ... | 09/25/2001 |
| 6285060 | Barrier accumulation-mode MOSFET In a trench-gated MOSFET, a lightly doped drift region of the N-type drain lies in the mesa between the trenches. The gate is doped with N-type material so that depletion regions are formed in the drift region when the gate voltage is equal to zero. The d... | 09/04/2001 |
| 6274451 | Method of fabricating a gate-control electrode for an IGBT transistor This method of fabricating a gate-control electrode (28) for an insulated-gate bipolar transistor, from a plate of electrically conducting material which is covered with an electrically insulating layer (22) and, on one of its large faces, delimits a conn... | 08/14/2001 |
| 6273950 | SiC device and method for manufacturing the same A method for manufacturing a device of silicon carbide (SiC) and a single crystal thin film, which are wide band gap semiconductor materials and can be applied to semiconductor devices such as high power devices, high temperature devices, and environmenta... | 08/14/2001 |
| 6242288 | Anneal-free process for forming weak collector The collector (anode) of a non punch through IGBT formed in a float zone silicon monocrystaline wafer is formed with a DMOS top structure and is thereafter ground at its bottom surface to a less than 250 micron thickness. A shallow P type implant is then ... | 06/05/2001 |
| 6228719 | MOS technology power device with low output resistance and low capacitance, and related manufacturing process A MOS-gated power device includes a plurality of elementary functional units, each elementary functional unit including a body region of a first conductivity type formed in a semiconductor material layer of a second conductivity type having a first resist... | 05/08/2001 |
| 6214107 | Method for manufacturing a SiC device A method for manufacturing a device of silicon carbide (SiC) and a single crystal thin film, which are wide band gap semiconductor materials and can be applied to semiconductor devices such as high power devices, high temperature devices, and environmenta... | 04/10/2001 |
