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| Number | Title | Issue Date |
| 8133786 | Transistors with laterally extended active regions and methods of fabricating same A transistor and method of fabricating the transistor are disclosed. The transistor is disposed in an active region of a substrate defined by an isolation region and includes a gate electrode and associated source/drain regions. The isolation region includes an uppe... | 03/13/2012 |
| 8053316 | Method of fabricating vertical channel transistor A method of fabricating a vertical channel transistor includes: forming a line type active pattern on a substrate so as to extend in a first horizontal direction; forming a vertical channel isolating the active pattern in a second horizontal direction intersecting t... | 11/08/2011 |
| 7994008 | Transistor device with two planar gates and fabrication process A planar transistor device includes two independent gates (a first and second gates) along with a semiconductor channel lying between the gates. The semiconductor channel is formed of a first material. The channel includes opposed ends comprising dielectric zone wit... | 08/09/2011 |
| 7977193 | Trench-gate MOSFET with capacitively depleted drift region A trench-gate metal oxide semiconductor field-effect transistor includes a field plate that extends into a drift region of the transistor. The field plate is configured to deplete the drift region when the transistor is in the OFF-state. The field plate is formed in... | 07/12/2011 |
| 7919376 | CMOS transistor and method for manufacturing the same A method for manufacturing a CMOS transistor includes preparing a silicon substrate provided with a first buried layer, a second buried layer and a body, vertically forming device-isolation films inside the body, forming a first-type well inside the body arranged on... | 04/05/2011 |
| 7919375 | Semiconductor device and method for manufacturing the device A semiconductor device and a method for manufacturing the device capable of preventing an LDD region and a lower portion of the gate electrode from overlapping each other to achieve desirable device performance are disclosed. Embodiments relate to a semiconductor de... | 04/05/2011 |
| 7910440 | Semiconductor device and method for making the same A semiconductor device includes: a first trench that is formed in a semiconductor substrate; a gate oxide film that is formed on a surface of the first trench; and a trench gate electrode that is formed so as to bury the first trench via the gate oxide film. The sem... | 03/22/2011 |
| 7897465 | Semiconductor device having reduced sub-threshold leakage A semiconductor device fabricated in the semiconductor substrate includes a FinFET transistor having opposed source and drain pillars, and a fin interposed between the source and drain pillars. A cavity is formed in the semiconductor substrate extending at least par... | 03/01/2011 |
| 7897464 | Method of manufacturing semiconductor device A method of manufacturing a semiconductor device including a buried insulating film formed in a bottom part of a trench and a buried-type gate electrode formed in the trench, the method including selectively forming an insulating film in the bottom part of the trenc... | 03/01/2011 |
| 7867857 | Transistor and method for manufacturing same An improved coupling stability between the source region and the source electrode of the transistor is achieved. In the method for manufacturing the MOSFET, the p-type base region is formed in a semiconductor layer, and after the p-type base region is formed in the ... | 01/11/2011 |
| 7799643 | Method of fabricating semiconductor device having self-aligned contact plug Methods of fabricating a semiconductor device having a self-aligned contact plug are provided. Methods include forming a lower insulating layer on a semiconductor substrate, forming a plurality of interconnection patterns parallel to each other on the lower insulati... | 09/21/2010 |
| 7790552 | Method for fabricating semiconductor device with bulb-shaped recess gate A method for fabricating a semiconductor device includes forming a plurality of bulb-shaped recesses in a substrate, forming a gate insulation layer over the substrate including the bulb-shaped recesses, forming a patterned first conductive layer over sidewalls of a... | 09/07/2010 |
| 7781287 | Methods of manufacturing vertical channel semiconductor devices Vertical channel semiconductor devices include a semiconductor substrate with a pillar having an upper surface. An insulated gate electrode is around a periphery of the pillar. The insulated gate electrode has an upper surface at a vertical level lower than the uppe... | 08/24/2010 |
| 7723191 | Method of manufacturing semiconductor device having buried gate A method of manufacturing a semiconductor device having buried gates may include forming a stacked structure of sequentially stacked first mask patterns and second mask patterns with equal widths to expose active regions and isolation regions of a semiconductor subs... | 05/25/2010 |
| 7713823 | Semiconductor device with vertical channel transistor and method for fabricating the same In a high speed vertical channel transistor, a pillar structure is formed over a substrate, a gate electrode surrounds an outer wall of a lower portion of the pillar structure; and a word line extends in a direction to partially contact an outer wall of the gate ele... | 05/11/2010 |
| 7622354 | Integrated circuit and method of manufacturing an integrated circuit An integrated circuit including a memory device comprises an array portion comprising memory cells and conductive lines, an upper surface of the conductive lines being disposed beneath a surface of a semiconductor substrate, and a support portion comprising transist... | 11/24/2009 |
| 7611949 | Method of fabricating metal-oxide-semiconductor transistor A method of fabricating a metal-oxide-semiconductor (MOS) transistor is provided. First, a patterned hard mask layer with an opening therein is formed over the substrate. A spacer is formed on the sidewall of the patterned hard mask layer in the opening. An isotropi... | 11/03/2009 |
| 7598144 | Method for forming inter-poly dielectric in shielded gate field effect transistor A method of forming shielded gate trench FET includes the following steps. A trench is formed in a silicon region of a first conductivity type. A shield electrode is formed in a bottom portion of the trench. An inter-poly dielectric (IPD) including a layer of therma... | 10/06/2009 |
| 7592230 | Trench power device and method Means and methods are provided for trench TMOS devices (41-10, 11, 12), comprising, providing a first semiconductor (53, 53′) of a first composition having an upper surface (541), with a body portion (54) proximate the upper surf... | 09/22/2009 |
| 7592229 | Method for fabricating a recessed-gate MOS transistor device A method for fabricating a recessed-gate transistor is disclosed. A trench is recessed into a substrate. A poly/nitride spacer is formed on sidewalls of the trench. A trench bottom oxide is formed. The spacer is then stripped off. A source/drain doping region is for... | 09/22/2009 |
| 7470589 | Semiconductor device A trench-structure semiconductor device is highly reliable and has an increased resistance to hydrofluoric acid cleaning or other cleaning of an insulation film between a gate electrode, which is embedded in a trench, and source electrode. In a trench-structure semi... | 12/30/2008 |
| 7470588 | Transistors including laterally extended active regions and methods of fabricating the same A transistor includes a substrate and an isolation region disposed in the substrate. The isolation regions defines an active region comprising upper and lower active regions, the upper active region having a first width and the lower active region having a second wi... | 12/30/2008 |
| 7442609 | Method of manufacturing a transistor and a method of forming a memory device with isolation trenches A method of manufacturing a transistor. In one embodiment, the method includes forming a gate electrode by defining a gate groove in the substrate. A plate-like portion is defined in each of the trenches at a position adjacent to the groove so that the two plate-lik... | 10/28/2008 |
| 7427547 | Three-dimensional high voltage transistor and method for manufacturing the same A method for manufacturing a three-dimensional high voltage transistor is disclosed. According to the method, lengths and widths of channels are increased while the reducing transistor forming area on plane, and semiconductor devices are completely separated from ea... | 09/23/2008 |
| 7387931 | Semiconductor memory device with vertical channel transistor and method of fabricating the same In a semiconductor memory device having a vertical channel transistor a body of which is connected to a substrate and a method of fabricating the same, the semiconductor memory device includes a semiconductor substrate including a plurality of pillars arranged space... | 06/17/2008 |
| 7375395 | Vertical field-effect transistor in source-down structure The invention relates to a vertical field-effect transistor in source-down structure, in which the active zones (10, 7, 11) are introduced from trenches (5, 8, 9) into a semiconductor body (1), a source electrode (18) being connected via ... | 05/20/2008 |
| 7361558 | Method of manufacturing a closed cell trench MOSFET Embodiments of the present invention provide an improved closed cell trench metal-oxide-semiconductor field effect transistor (TMOSFET). The closed cell TMOSFET comprises a drain, a body region disposed above the drain region, a gate region disposed in the body regi... | 04/22/2008 |
| 7358565 | Semiconductor device having improved insulated gate bipolar transistor and method for manufacturing the same An n-type first base layer is formed on a semiconductor substrate 1 having a first major surface and a second major surface, and a p-type second base layer is formed thereon. Between the first base layer and the second base layer, a carrier stored layer is fo... | 04/15/2008 |
| 7354829 | Trench-gate transistor with ono gate dielectric and fabrication process therefor A trench-gate type transistor has a gate insulating film formed on an inner wall of a trench. The gate insulating film includes a first portion located on a wall of the trench and a second portion located on upper and bottom portions of the trench. The first portion... | 04/08/2008 |
| 7338862 | Methods of fabricating a single transistor floating body DRAM cell having recess channel transistor structure Methods of fabricating a single transistor floating body dynamic random access memory (DRAM) cell include forming a barrier layer on a semiconductor substrate. A body layer is formed on the barrier layer. An isolation layer is formed defining a floating body region ... | 03/04/2008 |
| 7332773 | Vertical device 4FEEPROM memory EEPROM memory devices and arrays are described that facilitate the use of vertical floating gate memory cells and select gates in NOR or NAND high density memory architectures. Memory embodiments of the present invention utilize vertical select gates and floating ga... | 02/19/2008 |
| 7319058 | Fabrication method of a non-volatile memory A fabrication method for a non-volatile memory is provided. To fabricate the non-volatile memory, a plurality of first trenches and second trenches are formed in a substrate, wherein the second trenches are disposed above the first trenches and cross over the first ... | 01/15/2008 |
| 7319059 | High density FET with self-aligned source atop the trench A method for manufacturing a power semiconductor device which includes forming a semiconductor region such as a polysilicon layer or epitaxially grown silicon over a region implanted with source implants and applying heat in a thermal step to cause the source implan... | 01/15/2008 |
| 7303961 | Method for producing a junction region between a trench and a semiconductor zone surrounding the trench A method for producing a junction region (2, 5, 6, 7) between a trench (3) and a semiconductor zone (2) surrounding the trench (3) in a trench semiconductor device (1) has the following steps: application of an oxidation barrier la... | 12/04/2007 |
| 7282762 | 4FEEPROM NROM memory arrays with vertical devices NROM EEPROM memory devices and arrays are described that facilitate the use of vertical NROM memory cells and select gates in NOR or NAND high density memory architectures. Memory embodiments of the present invention utilize vertical select gates and NROM memory cel... | 10/16/2007 |
| 7276762 | NROM flash memory devices on ultrathin silicon An NROM flash memory cell is implemented in an ultra-thin silicon-on-insulator structure. In a planar device, the channel between the source/drain areas is normally fully depleted. An oxide layer provides an insulation layer between the source/drain areas and the ga... | 10/02/2007 |
| 7273786 | Method for fabricating a semiconductor memory cell In order to be able to store information in a non-volatile fashion as compactly and as flexibly as possible in a semiconductor memory cell, the original gate region of a conventional memory transistor is removed, and a memory gate configuration having a plurality of... | 09/25/2007 |
| 7268043 | Semiconductor device and method of manufacturing the same A semiconductor device and a method of manufacturing the same is disclosed. A trench is formed in an active region of a semiconductor substrate. A doped layer is formed on the inner walls of the trench. The trench is filled up with a first semiconductor layer. A gat... | 09/11/2007 |
| 7265024 | DMOS device having a trenched bus structure A DMOS device having a trench bus structure thereof is introduced. The trench bus structure comprises a field oxide layer formed on a P substrate, and a trench extending from an top surface of the field oxide layer down to a lower portion of the P substrate. A gate ... | 09/04/2007 |
| 7259069 | Semiconductor device and method of manufacturing the same A semiconductor device and a method of manufacturing the same is disclosed. A trench is formed in an active region of a semiconductor substrate. A doped layer is formed on the inner walls of the trench. The trench is filled up with a first semiconductor layer. A gat... | 08/21/2007 |
