Celebrity Inventors
Mark Twain (Samuel L. Clemens) received Patent No. 121,992 for "An Improvement in Adjustable and Detachable Straps for Garments." He later received two more patents: one for a self-pasting scrapbook and one for a game to help players remember important historical dates.
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| Number | Title | Issue Date |
| 8187938 | Non-volatile memory device and method for fabricating the same A method for fabricating a non-volatile memory device includes alternately stacking a plurality of interlayer dielectric layers and a plurality of conductive layers over a substrate, etching the interlayer dielectric layers and the conductive layers to form a trench... | 05/29/2012 |
| 8105902 | Semiconductor device with vertical transistor and method for fabricating the same A semiconductor device with a vertical transistor includes a plurality of active pillars, a plurality of vertical gates surrounding sidewalls of the active pillars; a plurality of word lines having exposed sidewalls whose surfaces are higher than the active pillars ... | 01/31/2012 |
| 8097510 | Method of forming lateral trench gate FET with direct source-drain current path A method of forming a field effect transistor (FET) includes: forming a drift region comprising a stack of alternating conductivity type silicon layers; forming a drain region of a first conductivity type extending into the stack of alternating conductivity type sil... | 01/17/2012 |
| 8071450 | Method for forming voltage sustaining layer with opposite-doped islands for semiconductor power devices A method of manufacturing a semiconductor device includes preparing a semiconductor wafer with a substrate of a first conductivity type and forming a first epitaxial layer of the first conductivity type on the substrate. The first epitaxial layer has a first thickne... | 12/06/2011 |
| 7998816 | Method for fabricating semiconductor device having vertical gate A method for fabricating a semiconductor device includes forming buried bit lines separated from each other by a trench in a substrate, forming a plurality of first pillar holes that expose a top surface of the substrate, forming first active pillars buried in the f... | 08/16/2011 |
| 7858475 | Method for manufacturing a vertical transistor that includes a super junction structure A manufacturing method of a semiconductor device includes: forming multiple trenches on a semiconductor substrate; forming a second conductive type semiconductor film in each trench to provide a first column with the substrate between two trenches and a second colum... | 12/28/2010 |
| 7851309 | Selective epitaxy vertical integrated circuit components and methods Integrated circuit components are described that are formed using selective epitaxy such that the integrated circuit components, such as transistors, are vertically oriented. These structures have regions that are doped in situ during selective epitaxial growth of t... | 12/14/2010 |
| 7820511 | Normally-off integrated JFET power switches in wide bandgap semiconductors and methods of making Wide bandgap semiconductor devices including normally-off VJFET integrated power switches are described. The power switches can be implemented monolithically or hybridly, and may be integrated with a control circuit built in a single- or multi-chip wide bandgap powe... | 10/26/2010 |
| 7807535 | Methods of forming layers comprising epitaxial silicon The invention includes methods of forming layers comprising epitaxial silicon. In one implementation, an opening is formed within a first material received over a monocrystalline material. Opposing walls, of a second material, are formed within the opening which are... | 10/05/2010 |
| 7767527 | Method for producing a vertical transistor component A method for producing a vertical transistor component includes steps of providing a semiconductor substrate, applying an auxiliary layer to the semiconductor substrate, and patterning the auxiliary layer for the purpose of producing at least one trench which extend... | 08/03/2010 |
| 7759199 | Stressor for engineered strain on channel A semiconductor substrate having recesses filled with heteroepitaxial silicon-containing material with different portions having different impurity concentrations. Strained layers can fill recessed source/drain regions in a graded, bottom-up fashion. Layers can also... | 07/20/2010 |
| 7736977 | Semiconductor device and a method for manufacturing therefor An object of the present invention is to provide a semiconductor device capable of radiating electron-beams only to a desired region without forming a layer for restricting the radiating rays. A source electrode 22 made of aluminum prevents the generation of ... | 06/15/2010 |
| 7709327 | Methods of forming semiconductor-on-insulator substrates, and integrated circuitry Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of mater... | 05/04/2010 |
| 7709326 | Methods of forming layers comprising epitaxial silicon The invention includes methods of forming layers comprising epitaxial silicon. In one implementation, an opening is formed within a first material received over a monocrystalline material. Opposing sidewalls of the opening are lined with a second material, with mono... | 05/04/2010 |
| 7618865 | Method in the fabrication of a monolithically integrated vertical device on an SOI substrate A method in the fabrication of a monolithically integrated vertical device on an SOI substrate comprises the steps of providing an SOI substrate including, from bottom to top, a silicon bulk material, an insulating layer, and an monocrystalline silicon layer; formin... | 11/17/2009 |
| 7598141 | Method of fabricating static random access memory A method of fabricating a static random access memory device includes selectively removing an insulating film and growing a single crystalline silicon layer using selective epitaxy growth, the single crystalline silicon layer being grown in a portion from which the ... | 10/06/2009 |
| 7598142 | CMOS device with dual-epi channels and self-aligned contacts A CMOS device having dual-epi channels comprises a first epitaxial region formed on a substrate, a PMOS device formed on the first epitaxial region, a second epitaxial region formed on the substrate, wherein the second epitaxial region is formed from a different mat... | 10/06/2009 |
| 7595242 | Method of manufacturing a superjunction power MOSFET with self-aligned trench gate A trench gate type power transistor of high performance is provided. A trench gate as a gate electrode is formed in a super junction structure comprising a drain layer and an epitaxial layer. In this case, the gate electrode is formed in such a manner that an upper ... | 09/29/2009 |
| 7550351 | Structure and method for creation of a transistor The invention is directed to an improved transistor that reduces dopant cross-diffusion and improves chip density. A first embodiment of the invention comprises gate electrode material partially removed at a junction of a first gate electrode region comprised of gat... | 06/23/2009 |
| 7514323 | Vertical SOI trench SONOS cell A semiconductor memory device in which a vertical trench semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell is created in a semiconductor-on-insulator (SOI) substrate is provided that allows for the integration of dense non-volatile random access me... | 04/07/2009 |
| 7514324 | Selective epitaxy in vertical integrated circuit Integrated circuit components are described that are formed using selective epitaxy such that the integrated circuit components, such as transistors, are vertically oriented. These structures have regions that are doped in situ during selective epitaxial growth of t... | 04/07/2009 |
| 7491610 | Fabrication method A process and an architecture related to a vertical MOSFET device and a capacitor for use in integrated circuits. The integrated circuit structure includes a semiconductor layer with a major surface and further including a first doped region formed in the surface. A... | 02/17/2009 |
| 7439136 | Method of forming a layer comprising epitaxial silicon The invention includes methods of forming epitaxial silicon-comprising material and methods of forming vertical transistors. In one implementation, a method of forming epitaxial silicon-comprising material includes providing a substrate comprising monocrystalline ma... | 10/21/2008 |
| 7432161 | Fabrication of optical-quality facets vertical to a (001) orientation substrate by selective epitaxial growth Methods for forming {110} type facets on a (001) oriented substrate of Group III-V compounds and Group IV semiconductors using selective epitaxial growth is provided. The methods include forming a dielectric film on a (100) substrate. The dielectric film can then be... | 10/07/2008 |
| 7374990 | Vertical wrap-around-gate field-effect-transistor for high density, low voltage logic and memory array A vertical transistor having a wrap-around-gate and a method of fabricating such a transistor. The wrap-around-gate (WAG) vertical transistors are fabricated by a process in which source, drain and channel regions of the transistor are automatically defined and alig... | 05/20/2008 |
| 7371645 | Method of manufacturing a field effect transistor device with recessed channel and corner gate device Fabrication of recessed channel array transistors (RCAT) with a corner gate device includes forming pockets between a semiconductor fin that includes a gate groove and neighboring shallow trench isolations that extend along longs sides of the semiconductor fin. A pr... | 05/13/2008 |
| 7368334 | Silicon-on-insulator chip with multiple crystal orientations A silicon-on-insulator chip includes an insulator layer, typically formed over a substrate. A first silicon island with a surface of a first crystal orientation overlies the insulator layer and a second silicon island with a surface of a second crystal orientation a... | 05/06/2008 |
| 7361556 | Method of fabricating semiconductor side wall fin A double gated silicon-on-insulator (SOI) MOSFET is fabricated by forming epitaxially grown channels, followed by a damascene gate. The double gated MOSFET features narrow channels, which increases current drive per layout width and provides low out conductance.... | 04/22/2008 |
| 7361970 | Method for production of a buried stop zone in a semiconductor component and semiconductor component comprising a buried stop zone A method for the production of a stop zone in a doped zone of a semiconductor body having a first side and a second side, comprises the following method steps: applying a mask having cutouts to one of the sides of the semiconductor... | 04/22/2008 |
| 7354806 | Semiconductor device structure with active regions having different surface directions and methods Semiconductor structure and method to simultaneously achieve optimal stress type and current flow for both nFET and pFET devices, and for gates orientated in one direction, are disclosed. One embodiment of the method includes bonding a first wafer having a first sur... | 04/08/2008 |
| 7354826 | Method for forming memory array bitlines comprising epitaxially grown silicon and related structure According to one exemplary embodiment, a method of fabricating a bitline in a memory array includes forming a trench in a substrate, where the trench has sidewalls and a bottom surface. The method further includes performing a selective epitaxial process to partiall... | 04/08/2008 |
| 7339241 | FinFET structure with contacts A FinFET, which by its nature has both elevated source/drains and an elevated channel that are portions of an elevated semiconductor portion that has parallel fins and one source/drain on one side of the fins and another source/drain on the other side of the fins, h... | 03/04/2008 |
| 7314799 | Self-aligned trench field effect transistors with regrown gates and bipolar junction transistors with regrown base contact regions and methods of making Junction field-effect transistors with vertical channels and self-aligned regrown gates and methods of making these devices are described. The methods use techniques to selectively grow and/or selectively remove semiconductor material to form a p-n junction gate alo... | 01/01/2008 |
| 7303966 | Semiconductor device and method of manufacturing the same Provided are a semiconductor device and a method of manufacturing the same. The method includes the steps of: forming a first silicon layer on a semiconductor substrate; patterning the first silicon layer formed on the semiconductor substrate, and exposing a channel... | 12/04/2007 |
| 7300837 | FinFET transistor device on SOI and method of fabrication A FinFET transistor on SOI device and method of fabrication is provided. At least two FinFET fins each having an upper poly-silicate glass portion and a lower silicon portion are formed using spacer patterning technology. Each fin is formed on a sacrificial SiN mask... | 11/27/2007 |
| 7285825 | Element formation substrate for forming semiconductor device A support-side substrate having a thermal oxide film on the major surface is bonded to an active-layer-side substrate having a thermal oxide film on the major surface while making the major surfaces oppose each other. The active-layer-side substrate and part of the ... | 10/23/2007 |
| 7279710 | Structure and method of fabricating a transistor having a trench gate An integrated circuit transistor is fabricated with a trench gate having nonconductive sidewalls. The transistor is surrounded by an isolation trench filled with a nonconductive material. The sidewalls of the gate trench are formed of the nonconductive material and ... | 10/09/2007 |
| 7276416 | Method of forming a vertical transistor The invention includes methods of forming epitaxial silicon-comprising material and methods of forming vertical transistors. In one implementation, a method of forming epitaxial silicon-comprising material includes providing a substrate comprising monocrystalline ma... | 10/02/2007 |
| 7271066 | Semiconductor device and a method of manufacturing the same Disclosed are a semiconductor devices and method of fabricating the same. Anti-etch films are formed in the top corners of the device isolation film using a material that has a different etch selectivity ratio from nitride or oxide and is not etched in an oxide gate... | 09/18/2007 |
| 7271067 | Voltage sustaining layer with opposite-doped islands for semiconductor power devices A semiconductor high-voltage device comprising a voltage sustaining layer between a n+-region and a p+-region is provided, which is a uniformly doped n (or p)-layer containing a plurality of floating p (or n)-islands. The effect of the floating islands is to absorb ... | 09/18/2007 |
