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| Number | Title | Issue Date |
| 8187937 | Semiconductor component and method for producing the same A method for producing a semiconductor component has the following step: the front side (101) of the semiconductor body (100) is irradiated with high-energy particles using the terminal electrode (40) as a mask, in order to produce recombination... | 05/29/2012 |
| 8168495 | Carbon nanotube high frequency transistor technology A technique of the invention reduces significantly the distance between the gate and single-walled carbon nanotubes to improve performance and efficiency of a carbon nanotube transistor device. Without using a porous template structure, single-walled carbon nanotube... | 05/01/2012 |
| 8163618 | Power MOSFET device structure for high frequency applications This invention discloses a new switching device supported on a semiconductor that includes a drain disposed on a first surface and a source region disposed near a second surface of said semiconductor opposite the first surface. The switching device further includes ... | 04/24/2012 |
| 8138046 | Process for fabricating a nanowire-based vertical transistor structure The invention relates to a process for fabricating a vertical transistor structure. On a substrate (10), is a first conductive layer (11), providing the source or drain electrode function, and an upper conductive layer (17), providing the drain ... | 03/20/2012 |
| 8138048 | Semiconductor storage device It is intended to provide a semiconductor device having a reduced thickness of a silicon nitride film on an outer periphery of a gate electrode of an SGT. A semiconductor device of the present invention is constructed using a MOS transistor which has a structure whe... | 03/20/2012 |
| 8138047 | Super junction semiconductor device In the specification and drawing a super junction semiconductor device is disclosed. The super junction semiconductor device comprises a P-type layer, a N+ substrate, a N-type layer, a silicon dioxide layer and a P+ layer. The N+ sub... | 03/20/2012 |
| 8133784 | Method of fabricating non-volatile memory device having vertical structure A method of fabricating a non-volatile memory device according to an example embodiment may include etching a plurality of sacrificial films and insulation films to form a plurality of first openings that expose a plurality of first portions of a semiconductor subst... | 03/13/2012 |
| 8129244 | Method for fabricating semiconductor device A method for fabricating a semiconductor device includes forming a plurality of first trenches by etching a substrate, forming a plurality of buried bit lines in the first trenches, forming a plurality of second trenches to expose at least one sidewall of the buried... | 03/06/2012 |
| 8124480 | Methods of fabricating silicon carbide devices incorporating multiple floating guard ring edge terminations Edge termination for silicon carbide devices has a plurality of concentric floating guard rings in a silicon carbide layer that are adjacent and spaced apart from a silicon carbide-based semiconductor junction. An insulating layer, such as an oxide, is provided on t... | 02/28/2012 |
| 8124479 | Diffusing impurity ions into pillars to form vertical transistors A method for manufacturing a semiconductor device that includes forming a pillar pattern including a sidewall contact over a semiconductor substrate; forming a silicon layer in a lower portion disposed between the pillar patterns; implanting ions into the silicon la... | 02/28/2012 |
| 8124478 | Method for fabricating flash memory device having vertical floating gate A method for fabricating a flash memory device includes forming a control gate having a hollow donut shape over an insulation layer formed over a substrate. The method also includes forming an inter-poly dielectric of a spacer shape on an inner wall of the control g... | 02/28/2012 |
| 8119484 | DRAM with nanofin transistors One aspect of the present subject matter relates to a memory. A memory embodiment includes a nanofin transistor having a first source/drain region, a second source/drain region above the first source/drain region, and a vertically-oriented channel region between the... | 02/21/2012 |
| 8110466 | Cross OD FinFET patterning A method of forming an integrated circuit structure includes providing a semiconductor substrate; providing a first lithography mask, a second lithography mask, and a third lithography mask; forming a first mask layer over the semiconductor substrate, wherein a patt... | 02/07/2012 |
| 8105901 | Method for double pattern density A method deposits an undoped silicon layer on a primary layer, deposits a cap layer on the undoped silicon layer, patterns a masking layer on the cap layer, and patterns the undoped silicon layer into silicon mandrels. The method incorporates impurities into sidewal... | 01/31/2012 |
| 8093127 | Method for forming a vertical transistor having tensile layers A vertical transistor includes a semiconductor substrate provided with a pillar type active pattern over the surface thereof. A first tensile layer is formed over the semiconductor substrate and around the lower end portion of the pillar type active pattern, and a s... | 01/10/2012 |
| 8080458 | Semiconductor device and manufacturing method thereof A method of manufacturing a semiconductor device includes the steps of forming a first columnar semiconductor layer on a substrate forming a first flat semiconductor layer forming a first semiconductor layer of a second conductive type, and forming a first insulatin... | 12/20/2011 |
| 8053313 | Semiconductor device and method of fabricating the same In a method of fabricating a semiconductor device on a substrate having a pillar pattern, a gate electrode is formed on the pillar pattern without etching the latter. A conductive pattern is filled between adjacent pillar patterns, a spacer is formed above the condu... | 11/08/2011 |
| 8053314 | Asymmetric field effect transistor structure and method Disclosed are embodiments of an asymmetric field effect transistor structure and a method of forming the structure in which both series resistance in the source region (Rs) and gate to drain capacitance (Cgd) are reduced in order to provide opt... | 11/08/2011 |
| 8048741 | Semiconductor memory device and method of fabricating the same A semiconductor memory device includes: a semiconductor substrate, on which an impurity diffusion layer is formed in a cell array area; a gate wiring stack body formed on the cell array area, in which multiple gate wirings are stacked and separated from each other w... | 11/01/2011 |
| 8048740 | Vertical MOS transistor and method therefor In one embodiment, a vertical MOS transistor is formed without a thick field oxide and particularly without a thick field oxide in the termination region of the transistor. ... | 11/01/2011 |
| 8039346 | Insulated gate silicon carbide semiconductor device and method for manufacturing the same An insulated gate silicon carbide semiconductor device is provided having small on-resistance in a structure obtained by combining the SIT and MOSFET structures having normally-off operation. The device includes an n− semiconductor layer on an SiC n | 10/18/2011 |
| 8030162 | Silicon carbide semiconductor device and manufacturing method thereof A silicon carbide semiconductor device is fabricated by forming an amorphous layer in a semiconductor layer of a silicon carbide substrate at a boundary between a cell forming area and an outer peripheral area, forming an outer peripheral insulating film over the se... | 10/04/2011 |
| 8026141 | Method of producing semiconductor In a conventional SGT production method, during dry etching for forming a pillar-shaped silicon layer and a gate electrode, an etching amount cannot be controlled using an end-point detection process, which causes difficulty in producing an SGT while stabilizing a h... | 09/27/2011 |
| 8012832 | Process for manufacturing a multi-drain electronic power device integrated in semiconductor substrate and corresponding device A process manufactures a multi-drain power electronic device integrated on a semiconductor substrate of a first type of conductivity whereon a drain semiconductor layer is formed. The process includes: forming a first semiconductor epitaxial layer of the first type ... | 09/06/2011 |
| 8003464 | Methods of manufacturing semiconductor device having recess channel array transistor Methods of manufacturing a semiconductor device having an RCAT are provided. The method includes forming a first recess having a first depth formed in an active region of a semiconductor substrate, and a second recess having a second depth that is less than the firs... | 08/23/2011 |
| 7998815 | Shallow trench isolation Shallow trench isolation methods are disclosed. In a particular embodiment, a method includes implanting oxygen under a bottom surface of a narrow trench of a silicon substrate and performing a high-temperature anneal of the silicon substrate to form a buried oxide ... | 08/16/2011 |
| 7989292 | Method of fabricating a semiconductor device with a channel formed in a vertical direction In a method of fabricating a semiconductor device on a substrate which includes a plurality of pillar patterns, an impurity region between adjacent pillar patterns, a gate electrode on each pillar pattern, a first capping layer covering the gate electrode, and a sep... | 08/02/2011 |
| 7960232 | Methods of designing an integrated circuit on corrugated substrate By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-powe... | 06/14/2011 |
| 7955929 | Method of forming a semiconductor device having an active area and a termination area A method of forming a semiconductor device having an active area and a termination area surrounding the active area comprises providing a semiconductor substrate, providing a semiconductor layer of a first conductivity type over the semiconductor substrate and formi... | 06/07/2011 |
| 7951676 | Semiconductor device and method for the production of a semiconductor device The semiconductor device has a semiconductor body with a semiconductor device structure. The semiconductor device structure has a first electrode, a second electrode and a gate electrode. The gate electrode is designed to form a conductive channel region. An insulat... | 05/31/2011 |
| 7935598 | Vertical channel transistor and method of fabricating the same A vertical channel transistor includes a plurality of active pillar patterns extending perpendicularly from the top surface of the substrate toward an upper part. A gate insulating layer is deposited on the side wall of the active pillar pattern and serves as an ion... | 05/03/2011 |
| 7923329 | Method for manufacturing a semiconductor device A method for manufacturing a semiconductor device includes forming a spin-on-carbon (SOC) film that facilitates a low temperature baking process, can prevent collapse of vertical transistors while forming a bit line, thereby providing a more simple manufacturing met... | 04/12/2011 |
| 7910437 | Method of fabricating vertical channel semiconductor device A method for fabricating a semiconductor device may include: forming an outer trench, including: a first trench, and a second trench formed under the first trench, the second trench being formed by etching a substrate, forming a dielectric layer, which fills the sec... | 03/22/2011 |
| 7906398 | Method of fabricating semiconductor device In a method of fabricating a semiconductor device having vertical channels and a method of patterning a gate electrode of such semiconductor device, an initial conductive layer is removed by multiple etching processes. ... | 03/15/2011 |
| 7897459 | Semiconductor device and manufacturing method thereof A through electrode is formed prior to fabricating a semiconductor device by using a standard manufacturing method. Aside face of the through electrode is insulated from a semiconductor substrate by an insulating film, while the top face thereof is covered with a pr... | 03/01/2011 |
| 7892923 | Power field effect transistor and manufacturing method thereof A method of manufacturing a vertical power MOS transistor on a wide band gap semiconductor substrate having a wide band gap superficial semiconductor layer, including the steps of forming a screening structure on the superficial semiconductor layer that leaves a plu... | 02/22/2011 |
| 7892924 | Method for making a charge balanced multi-nano shell drift region for superjunction semiconductor device A method is disclosed for making a substantially charge balanced multi-nano shell drift region (MNSDR) for superjunction semiconductor devices atop a base substrate. The MNSDR has numerous concentric nano shell members NSM1, NSM2, . . . , NSM | 02/22/2011 |
| 7888212 | Semiconductor device and method of manufacturing the same In a well region, an irregular structure is formed in a gate width direction, and a gate electrode is formed in concave portions and on top surfaces of convex portions via an insulating film. Upper and lower source regions are formed on one side of the gate electrod... | 02/15/2011 |
| 7883968 | Field effect transistor and its manufacturing method The present invention is an object to provide a high-performance vertical field effect transistor having a microminiaturized structure in which the distance between the gate and the channel is made short not through a microfabrication process, having a large gate ca... | 02/08/2011 |
| 7879675 | Field effect transistor with metal source/drain regions A semiconductor device comprising a gate electrode formed on a gate dielectric layer formed on a semiconductor film. A pair of source/drain regions are formed adjacent the channel region on opposite sides of the gate electrode. The source and drain regions each comp... | 02/01/2011 |
