Did You Know...
...that Robert Adler has the dubious distinction of being the Father of the Couch Potato? Back in 1955 Adler was employed by what was then Zenith Radio Corp., where he was charged to invent something that would allow viewers to turn down the TV volume without leaving their chairs. After a series of flops (such as a wired contraption that people tripped over), Adler hit on the idea of using sound waves. Thus the Remote Control was born...
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| Number | Title | Issue Date |
| 8133783 | Semiconductor device having different structures formed simultaneously In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method includes forming a portion of the unidirectional transistor and a portion of a bidirectional transistor in or over a semiconductor... | 03/13/2012 |
| 8114742 | Nonvolatile semiconductor memory and method of manufacturing the same A method of forming a nonvolatile memory device which includes forming a first gate electrode on a gate insulating film formed on a semiconductor substrate. The first gate electrode having a lower portion formed on the gate insulating film and an upper portion havin... | 02/14/2012 |
| 8110465 | Field effect transistor having an asymmetric gate electrode The gate electrode of a metal oxide semiconductor field effect transistor (MOSFET) comprises a source side gate electrode and a drain side gate electrode that abut each other near the middle of the channel. In one embodiment, the source side gate electrode comprises... | 02/07/2012 |
| 8076201 | Method of manufacturing flash memory device A method of manufacturing a flash memory device according to an embodiment includes forming a second oxide layer pattern having a mask pattern buried therein on a first nitride layer pattern and a first oxide layer stack on a semiconductor substrate; forming first p... | 12/13/2011 |
| 8043915 | Pitch multiplied mask patterns for isolated features Crisscrossing spacers formed by pitch multiplication are used as a mask to form isolated features, such as contacts vias. A first plurality of mandrels are formed on a first level and a first plurality of spacers are formed around each of the mandrels. A second plur... | 10/25/2011 |
| 8003463 | Structure, design structure and method of manufacturing dual metal gate Vt roll-up structure A structure, design structure and method of manufacturing is provided for a dual metal gate Vt roll-up structure, e.g., multi-work function metal gate. The method of manufacturing the multi-work function metal gate structure comprises forming a first type of metal w... | 08/23/2011 |
| 7977191 | Method for fabricating flash memory device A method of forming a flash memory device includes forming a plurality of memory gates over a semiconductor substrate, forming an oxide film over the uppermost surface and sidewalls of the memory gates and then forming a plurality of selective gates on sidewalls of ... | 07/12/2011 |
| 7927951 | Non-volatile memory device and method of operating the same A non-volatile memory device includes a semiconductor substrate, first and second control gates, and first and second charge storage patterns. The semiconductor substrate includes a protruding active pin having a source region, a drain region and a channel region lo... | 04/19/2011 |
| 7902024 | Nonvolatile semiconductor device including a floating gate, method of manufacturing the same and associated systems A memory device includes a first floating gate electrode on a substrate between adjacent isolation layers in the substrate, at least a portion of the first floating gate protruding above a portion of the adjacent isolation layers, a second floating gate electrode, e... | 03/08/2011 |
| 7888211 | Method of manufacturing flash memory device A method of manufacturing a flash memory device includes preparing a semiconductor substrate comprising a cell area and a peripheral area, forming a first well and an oxide-nitride-oxide (ONO) layer in the cell area, forming a second well in the peripheral area of t... | 02/15/2011 |
| 7838363 | Method of forming a split gate non-volatile memory cell A method forms a split gate memory cell by providing a semiconductor substrate and forming an overlying select gate. The select gate has a predetermined height and is electrically insulated from the semiconductor substrate. A charge storing layer is subsequently for... | 11/23/2010 |
| 7785966 | Method for fabricating floating gates structures with reduced and more uniform forward tunneling voltages An improved method for fabricating floating gate structures of flash memory cells having reduced and more uniform forward tunneling voltages. The method may include the steps of: forming at least two floating gates over a substrate; forming a mask over each of the f... | 08/31/2010 |
| 7759197 | Method of forming isolated features using pitch multiplication Crisscrossing spacers formed by pitch multiplication are used as a mask to form isolated features, such as contacts vias. A first plurality of mandrels are formed on a first level and a first plurality of spacers are formed around each of the mandrels. A second plur... | 07/20/2010 |
| 7723188 | Non-volatile memory devices and methods of forming the same A non-volatile memory device includes an upwardly protruding fin disposed on a substrate and a control gate electrode crossing the fin. A floating gate is interposed between the control gate electrode and the fin and includes a first storage gate and a second storag... | 05/25/2010 |
| 7704835 | Method of forming a selective spacer in a semiconductor device A selective spacer for semiconductor and MEMS devices and method of manufacturing the same. In an embodiment, a selective spacer is formed adjacent to a first non-planar body having a greater sidewall height than a second non-planar semiconductor body in a self-alig... | 04/27/2010 |
| 7700439 | Silicided nonvolatile memory and method of making same A memory device is formed on a semiconductor substrate. A select gate electrode and a control gate electrode are formed adjacent to one another. One of either the select gate electrode or the control gate electrodes is recessed with respect to the other. The recess ... | 04/20/2010 |
| 7601593 | Flash memory with metal-insulator-metal tunneling program and erase The flash memory cell comprises a sense transistor that has a pair of source/drain lines and a control gate. A coupling metal-insulator-metal capacitor is created between the control gate and a read wordline. A tunneling metal-insulator-metal capacitor is created be... | 10/13/2009 |
| 7601594 | Method for fabricating semiconductor memory A method for fabricating a semiconductor memory, the method including: forming an element isolation region in a concave portion of the semiconductor substrate; forming a layer of a gate electrode material so as to cover the concave portion and the element isolation ... | 10/13/2009 |
| 7585731 | Semiconductor integrated circuit device and its manufacturing method A method of manufacturing a semiconductor integrated circuit device is provided including providing a substrate with projecting island regions formed in stripes, with first regions of the substrate adjacent the projecting island regions and with a conductive film co... | 09/08/2009 |
| 7579243 | Split gate memory cell method Split gate memory cell formation includes forming a sacrificial layer over a substrate. The sacrificial layer is patterned to form a sacrificial structure with a first sidewall and a second sidewall. A layer of nanocrystals is formed over the substrate. A first laye... | 08/25/2009 |
| 7572702 | Split gate type non-volatile memory device Embodiments relate to a gate structure of a split gate-type non-volatile memory device and a method of manufacturing the same. In embodiments, the split gate-type non-volatile memory device may include a device isolation layer formed on a semiconductor substrate in ... | 08/11/2009 |
| 7557005 | Semiconductor device and a method of manufacturing the same In a semiconductor device which includes a split-gate type memory cell having a control gate and a memory gate, a low withstand voltage MISFET and a high withstand voltage MISFET, variations of the threshold voltage of the memory cell are suppressed. A gate insulati... | 07/07/2009 |
| 7488649 | Method of manufacturing split gate type non-volatile memory device A method of manufacturing a split gate type non-volatile memory device includes the steps of defining an active region on a semiconductor substrate; forming a pair of first conductive film patterns, each having an electric charge storage layer interposed between the... | 02/10/2009 |
| 7462539 | Direct tunneling memory with separated transistor and tunnel areas A semiconductor device has: an isolation region formed on a semiconductor substrate and defining a continuous active region including a select transistor region and a direct tunnel element region; a gate insulating film formed on a channel region of the select trans... | 12/09/2008 |
| 7439157 | Isolation trenches for memory devices A method includes removing a portion of a substrate to define an isolation trench; forming a first dielectric layer on exposed surfaces of the substrate in the trench; forming a second dielectric layer on at least the first dielectric layer, the second dielectric la... | 10/21/2008 |
| 7435683 | Apparatus and method for selectively recessing spacers on multi-gate devices Embodiments of an apparatus and methods for fabricating a spacer on one part of a multi-gate transistor without forming a spacer on another part of the multi-gate transistor are generally described herein. Other embodiments may be described and claimed. ... | 10/14/2008 |
| 7436020 | Flash memory with metal-insulator-metal tunneling program and erase The flash memory cell comprises a sense transistor that has a pair of source/drain lines and a control gate. A coupling metal-insulator-metal capacitor is created between the control gate and a read wordline. A tunneling metal-insulator-metal capacitor is created be... | 10/14/2008 |
| 7432159 | Electrically erasable programmable read-only memory (EEPROM) device and methods of fabricating the same An EEPROM device includes a device isolation layer disposed at a predetermined region of a semiconductor substrate to define active regions, a pair of control gates crossing the device isolation layers and an active region, a pair of selection gates interposed betwe... | 10/07/2008 |
| 7416945 | Method for forming a split gate memory device A method forms a split gate memory device. A layer of select gate material over a substrate is patterned to form a first sidewall. A sacrificial spacer is formed adjacent to the first sidewall. Nanoclusters are formed over the substrate including on the sacrificial ... | 08/26/2008 |
| 7378314 | Source side injection storage device with control gates adjacent to shared source/drain and method therefor A storage device has a two bit cell in which the select electrode is nearest the channel between two storage layers. Individual control electrodes are over individual storage layers. Adjacent cells are separated by a doped region that is shared between the adjacent ... | 05/27/2008 |
| 7378315 | Method for fabricating semiconductor device A method for fabricating a semiconductor device for a system on chip (SOC) for embodying a transistor for a logic device, an electrical erasable programmable read only memory (EEPROM) cell and a flash memory cell in one chip is provided. Floating gates of the EEPROM... | 05/27/2008 |
| 7374999 | Semiconductor device A semiconductor device includes a substrate including a high-voltage transistor area provided with a high-voltage transistor and a low-voltage transistor area provided with a low-voltage transistor; a LOCOS layer provided as a device isolation layer of the high-volt... | 05/20/2008 |
| 7371645 | Method of manufacturing a field effect transistor device with recessed channel and corner gate device Fabrication of recessed channel array transistors (RCAT) with a corner gate device includes forming pockets between a semiconductor fin that includes a gate groove and neighboring shallow trench isolations that extend along longs sides of the semiconductor fin. A pr... | 05/13/2008 |
| 7368373 | Method for manufacturing semiconductor devices and plug A method for manufacturing a semiconductor device is disclosed suitable for a substrate having a first conducting structure and a first dielectric layer, wherein the dielectric layer covers the first conductive structure. The method includes the steps of forming a s... | 05/06/2008 |
| 7366026 | Flash memory device and method for fabricating the same, and programming and erasing method thereof A flash memory device of SONOS structure and a method for fabricating the same, and programming and erasing operation methods, to improve reliability such as endurance and retention, are disclosed, which includes a first conductive type semiconductor substrate; an O... | 04/29/2008 |
| 7364970 | Method of making a multi-bit non-volatile memory (NVM) cell and structure A multi-bit non volatile memory cell includes a first floating gate sidewall spacer structure and a second floating gate sidewall spacer structure physically separated from the first floating gate sidewall spacer structure. Each floating gate sidewall spacer structu... | 04/29/2008 |
| 7361554 | Multi-bit non-volatile memory device, method of operating the same, and method of manufacturing the multi-bit non-volatile memory device Disclosed are a multi-bit non-volatile memory device, a method of operating the same, and a method of manufacturing the multi-bit non-volatile memory device. A unit cell of the multi-bit non-volatile memory device may be formed on a semiconductor substrate may inclu... | 04/22/2008 |
| 7354825 | Methods and apparatus to form gates in semiconductor devices A method of formation a gate in a semiconductor device includes forming a gate oxide layer and a sacrificial layer on a semiconductor substrate. The sacrificial layer is then selectively etched to form a sidewall opening. Next, a polycrystalline silicon layer is for... | 04/08/2008 |
| 7355241 | Non-volatile memory A non-volatile memory including a substrate, a select gate, two floating gates, a control gate, and a doped region is described. The select gate is disposed on the substrate. The two floating gates are disposed on both sides of the select gate, and the top surface o... | 04/08/2008 |
| 7351636 | Methods of forming split-gate non-volatile memory cells including raised oxide layers on field oxide regions A method of forming a split-gate non-volatile memory cell can include forming first and second adjacent floating gates self-aligned to a field oxide region therebetween. An oxide layer is formed covering the first and second adjacent floating gates and the field oxi... | 04/01/2008 |
