Class 438/262 - Including elongated source or drain region disposed under thick oxide regions (e.g., buried or diffused bitline, etc.)

Subclass of Class 438 - Semiconductor device manufacturing: process
Definition: Process for making a floating gate-type insulated gate field
No. of patents: 343
Last issue date: 10/11/2011

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Number	Title	Issue Date
8034684	Semiconductor device with improved overlay margin and method of manufacturing the same Semiconductor devices with an improved overlay margin and methods of manufacturing the same are provided. In one aspect, a method includes forming a buried bit line in a substrate; forming an isolation layer in the substrate to define an active region, the isolation...	10/11/2011
8012830	ORO and ORPRO with bit line trench to suppress transport program disturb Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line openings containing a bit line dielectric between the memory cells...	09/06/2011
7989291	Anisotropic stress generation by stress-generating liners having a sublithographic width A protruding structure having a linear edge is formed on a substrate. The protruding structure may be a gate line of a field effect transistor. A stress-generating liner is deposited on the substrate. A non-photosensitive self-assembling block copolymer layer contai...	08/02/2011
7951675	SI trench between bitline HDP for BVDSS improvement Memory devices having improved BVdss characteristics and methods of making the memory devices are provided. The memory devices contain bitline dielectrics on bitlines of a semiconductor substrate; first spacers adjacent the side surfaces of the bitline dielectrics a...	05/31/2011
7858473	Flash memory device and method of manufacturing the same A flash memory device having a spacer of a gate region formed in an oxide-nitride-oxide (ONO) structure and a source/drain region formed using the ONO structure. The outermost oxide in the ONO structure is removed and an interlayer insulating film is formed to ensur...	12/28/2010
7846796	Semiconductor devices including buried bit lines A semiconductor device includes a plurality of channel structures on a semiconductor substrate. A bit line groove having opposing sidewalls is defined between sidewalls of adjacent ones of the plurality of channel structures. A plurality of bit lines are formed on c...	12/07/2010
7846795	Bit line of a semiconductor device and method for fabricating the same A bit line of a semiconductor device includes a first interlayer dielectric film disposed on a semiconductor substrate, a plurality of bit line stacks disposed on the first interlayer dielectric film, a plurality of bit line spacers disposed on side walls of the bit...	12/07/2010
7811887	Forming silicon trench isolation (STI) in semiconductor devices self-aligned to diffusion Silicon trench isolation (STI) is formed between adjacent diffusions in a semiconductor device, such as between bitlines in a memory array. The STI may be self-aligned to the diffusions, and may prevent misaligned bitline (BL) contacts from contacting silicon outsid...	10/12/2010
7749840	Methods of forming a semiconductor device including buried bit line A method of forming a buried interconnection includes removing a semiconductor substrate to form a groove in the semiconductor substrate. A metal layer is formed on inner walls of the groove using an electroless deposition technique. A silicidation process is applie...	07/06/2010
7741179	Method of manufacturing flash semiconductor device A method of manufacturing a flash semiconductor device minimizes a loss of dopant caused by dopant out-diffusion. A trench is formed in a semiconductor substrate. At least one poly gate is formed in the semiconductor substrate including the trench. An RCS (Recess Co...	06/22/2010
7732279	Semiconductor device with improved overlay margin and method of manufacturing the same Semiconductor devices with an improved overlay margin and methods of manufacturing the same are provided. In one aspect, a method includes forming a buried bit line in a substrate; forming an isolation layer in the substrate to define an active region, the isolation...	06/08/2010
7713821	Thin silicon-on-insulator high voltage auxiliary gated transistor A silicon (Si)-on-insulator (SOI) high voltage transistor is provided with an associated fabrication process. The method provides a SOI substrate with a Si top layer. A control channel and an adjacent auxiliary channel are formed in the Si top layer. A control gate ...	05/11/2010
7687348	Semiconductor device and method of producing the same A semiconductor device includes a semiconductor substrate having an insulation layer and a semiconductor layer formed on the insulation layer; a channel area formed in the semiconductor layer; a gate electrode formed on the channel area; a source area formed in the ...	03/30/2010
7501322	Methods of forming non-volatile memory devices having trenches A semiconductor memory device includes a semiconductor substrate having a trench therein. First and second gate patterns are formed on a surface of the substrate adjacent the trench, a respective one of which is on a respective opposing side of the trench. A split s...	03/10/2009
7465632	Method for forming buried doped region A method for forming a buried doped region is provided. A first insulating layer is formed on a substrate and the first insulating layer is patterned to from an opening that extends in a first direction. A buried doped region is formed in the substrate exposed by th...	12/16/2008
7439134	Method for process integration of non-volatile memory cell transistors with transistors of another type A method for making a semiconductor device having non-volatile memory cell transistors and transistors of another type is provided. In the method, a substrate is provided having an NVM region, a high voltage (HV) region, and a low voltage (LV) region. The method inc...	10/21/2008
7439157	Isolation trenches for memory devices A method includes removing a portion of a substrate to define an isolation trench; forming a first dielectric layer on exposed surfaces of the substrate in the trench; forming a second dielectric layer on at least the first dielectric layer, the second dielectric la...	10/21/2008
7435647	NOR-type flash memory device and manufacturing method thereof A flash memory device that has a structure capable of preventing gate stack damage, and a method of manufacturing the same, is presented. The method includes forming a first photo resist pattern to open a common source region on a substrate where a shallow trench is...	10/14/2008
7435649	Floating-gate non-volatile memory and method of fabricating the same A floating gate non-volatile memory is composed of a semiconductor substrate within which active regions and isolation dielectrics are alternately arranged in a first direction; a word line extending in the first direction to intersect with the active regions and th...	10/14/2008
7429514	Use of selective oxidation to form asymmetrical oxide features during the manufacture of a semiconductor device A sidewall oxidation process for use during the formation of a transistor such as a flash memory cell allows for improved control of a gate oxide profile. The method comprises doping transistor source and drain regions to different doping levels, then performing a t...	09/30/2008
7416944	Flash EEPROM device and method for fabricating the same In a flash EEPROM device, and method for fabricating the same, no bit line contact is made, thereby minimizing a design rule between a contact and a gate. Thus, cell size may be reduced. The flash EEPROM device includes a semiconductor substrate having an active are...	08/26/2008
7384847	Methods of forming DRAM arrays The invention includes memory arrays, and methods which can be utilized for forming memory arrays. A patterned etch stop can be used during memory array fabrication, with the etch stop covering storage node contact locations while leaving openings to bitline contact...	06/10/2008
7381617	Method of fabricating flash memory device A method of fabricating flash memory devices includes the steps of forming a stop nitride film and an oxide film on a semiconductor substrate having a predetermined structure formed therein, forming trenches in the oxide film and the stop nitride film, forming barri...	06/03/2008
7374989	Flash memory and methods of fabricating the same Flash memory and methods of fabricating the same are disclosed. An illustrated example flash memory includes a first source formed within a semiconductor substrate; an epitaxial layer formed on an upper surface of the semiconductor substrate; an opening formed withi...	05/20/2008
7372098	Low power flash memory devices A buried bipolar junction is provided in a floating gate transistor flash memory device. During a write operation electrons are injected into a surface depletion region of the memory cell transistors. These electrons are accelerated in a vertical electric field and ...	05/13/2008
7371645	Method of manufacturing a field effect transistor device with recessed channel and corner gate device Fabrication of recessed channel array transistors (RCAT) with a corner gate device includes forming pockets between a semiconductor fin that includes a gate groove and neighboring shallow trench isolations that extend along longs sides of the semiconductor fin. A pr...	05/13/2008
7368350	Memory cell arrays and methods for producing memory cell arrays A method for fabricating stacked non-volatile memory cells and non-volatile memory cell arrays are disclosed. A semiconductor wafer is provided having a charge-trapping layer and a conductive layer deposited on the surface of the semiconductor wafer. Using a mask la...	05/06/2008
7358558	Flash memory device A floating gate of a flash memory device is formed in a moat formed in an isolation film. Therefore, an electric field applied between a control gate and a channel region upon cycling can be precluded or mitigated. A distance between the control gate and the channel...	04/15/2008
7354824	Fabrication method of non-volatile memory A method for fabricating a non-volatile memory is provided. A dielectric layer, a first conductive layer, and a mask layer are formed sequentially on a substrate and then patterned to form a number of openings and floating gates. In addition, spacers are formed on t...	04/08/2008
7338864	Memory device and method for fabricating the same Disclosed are a memory device and a method for fabricating the same. The memory device includes: a substrate provided with a trench; a bit line contact junction formed beneath the trench; a plurality of storage node contact junctions formed outside the trench; and a...	03/04/2008
7335558	Method of manufacturing NAND flash memory device A method of manufacturing a NAND flash memory device, including the steps of providing a semiconductor substrate in which a cell region and a select transistor region are defined; simultaneously forming a plurality of cell gates on the semiconductor substrate of the...	02/26/2008
7333370	Method to prevent bit line capacitive coupling Structures, systems and methods for memory cells utilizing trench bit lines formed within a buried layer are provided. A memory cell is formed in a triple well structure that includes a substrate, the buried layer, and an epitaxial layer. The substrate, buried layer...	02/19/2008
7332408	Isolation trenches for memory devices Methods and apparatus are provided. A first dielectric plug is formed in a portion of a trench that extends into a substrate of a memory device so that an upper surface of the first dielectric plug is recessed below an upper surface of the substrate. The first diele...	02/19/2008
7323742	Non-volatile memory integrated circuit A nonvolatile memory integrated circuit arrayed in rows and columns is disclosed. Parallel lines of implant N-type regions are formed in a P-well of a semiconductor substrate, with lines of oxide material isolating each pair of the lines. Columns of memory cells str...	01/29/2008
7323385	Method of fabricating flash memory device A method of fabricating flash memory devices includes the steps of forming a stop nitride film and an oxide film on a semiconductor substrate having a predetermined structure formed therein, forming trenches in the oxide film and the stop nitride film, forming barri...	01/29/2008
7309632	Method for fabricating a nonvolatile memory cell A method of fabricating a nonvolatile memory cell includes providing a substrate with a trench, with a sidewall where a tunnel oxide layer and a floating gate are successively formed, forming a control gate in the trench, performing a high density plasma deposition ...	12/18/2007
7309650	Memory device having a nanocrystal charge storage region and method A memory device having a metal nanocrystal charge storage structure and a method for its manufacture. The memory device may be manufactured by forming a first oxide layer on the semiconductor substrate, then disposing a porous dielectric layer on the oxide layer and...	12/18/2007
7300842	Method of fabricating a mask ROM A mask ROM and fabrication method thereof are disclosed, in which a bit line is formed of a conductive material such as polysilicon, by which a device size can be minimized, and by which resistance characteristics are enhanced. ...	11/27/2007
7291881	Bit line structure and method of fabrication The invention relates to a bit line structure having a surface bit line (DLx) and a buried bit line (SLx), the buried bit line (SLx) being formed in a trench with a trench insulation layer (6) and being connected to doping regions (10) with which conta...	11/06/2007
7279384	Semiconductor memory and method for manufacturing the same A semiconductor memory has plural cell transistors that are arranged in a matrix. The cell transistor comprises a P type silicon substrate, a control gate CG and a pair of electrically isolated floating gates. Plural projections are formed in the silicon substrate, ...	10/09/2007

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Class 438/262 - Including elongated source or drain region disposed under thick oxide regions (e.g., buried or diffused bitline, etc.)