Apparatus for Simulating a High Five
A self-righting hand-arm configuration which is adapted to pivot when struck by a user, thereby simulating a "high five."
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| Number | Title | Issue Date |
| 8178406 | Split gate device and method for forming A method of making a semiconductor device on a semiconductor layer includes forming a select gate, a recess, a charge storage layer, and a control gate. The select gate is formed have a first sidewall over the semiconductor layer. The recess is formed in the semicon... | 05/15/2012 |
| 8178407 | Systems and methods for a high density, compact memory array A memory array comprising vertical memory cells does not require any isolation layers between cells. Thus, a very compact, high density memory array can be achieved. Each memory cell in the memory array is configured to store 4 bits of data per cell. Multi-level cha... | 05/15/2012 |
| 8178408 | Methods of manufacturing charge trap-type non-volatile memory devices Some methods are directed to manufacturing charge trap-type non-volatile memory devices. An isolation layer pattern can be formed that extends in a first direction in a substrate. A recess unit is formed in the substrate by recessing an exposed surface of the substr... | 05/15/2012 |
| 8173506 | Method of forming buried gate electrode utilizing formation of conformal gate oxide and gate electrode layers A method of forming a buried gate electrode prevents voids from being formed in a silicide layer of the gate electrode. The method begins by forming a trench in a semiconductor substrate, forming a conformal gate oxide layer on the semiconductor in which the trench ... | 05/08/2012 |
| 8168494 | Trench MOS transistor and method of manufacturing the same Trench portions (10) are formed in a well (5) in order to provide unevenness in the well (5). A gate electrode (2) is formed via an insulating film (7) on the upper surface and inside of the trench portions (10). A source re... | 05/01/2012 |
| 8163617 | Vertical channel type non-volatile memory device and method for fabricating the same A method for fabricating a vertical channel type non-volatile memory device including forming a source region, alternately forming a plurality of interlayer dielectric layers and a plurality of conductive layers for a gate electrode over a substrate with the source ... | 04/24/2012 |
| 8153489 | Method for fabricating semiconductor device with buried gates A method for fabricating a semiconductor device, including forming a trench by etching a semiconductor substrate, forming a gate insulation layer over a surface of the trench, forming a gate conductive layer over the gate insulation layer, performing a first recess ... | 04/10/2012 |
| 8143123 | Methods of forming inter-poly dielectric (IPD) layers in power semiconductor devices A method for forming power semiconductor devices having an inter-electrode dielectric (IPD) layer inside a trench includes providing a semiconductor substrate with a trench, lining the sidewalls and bottom of the trench with a first layer of dielectric material, fil... | 03/27/2012 |
| 8129241 | Method for forming a shielded gate trench FET A method for forming a shielded gate field effect transistor (FET) includes forming a plurality of trenches in a semiconductor region and forming a shield electrode in a bottom portion of each trench. The method also includes forming a dielectric layer comprising a ... | 03/06/2012 |
| 8119482 | MOSFET using gate work function engineering for switching applications This invention discloses a new MOSFET device. The MOSFET device has an improved operation characteristic achieved by manufacturing a MOSFET with a higher gate work function by implementing a P-doped gate in an N-MOSFET device. The P-type gate increases the threshold... | 02/21/2012 |
| 8097509 | Method for manufacturing semiconductor device with a recessed channel A semiconductor device having a recessed channel and a method for manufacturing the same. The semiconductor device comprises a semiconductor substrate formed with an isolation layer defining an active region including a channel region and a junction region, a recess... | 01/17/2012 |
| 8093125 | Manufacturing method of capacitor in semiconductor device Example embodiment is provided to a method for manufacturing a semiconductor device, including forming a hard mask layer on a buried bit line and forming a storage node contact hole by using the selectivity between an interlayer insulating layer and the hard mask la... | 01/10/2012 |
| 8088660 | Method for producing a plug in a semiconductor body A method for producing an electrode in a semiconductor layer includes providing a substrate with a first surface and a second surface, forming a first trench having sidewalls and extending into the substrate from the first surface and forming a plug in the first tre... | 01/03/2012 |
| 8084325 | Semiconductor device and method for fabricating the same A semiconductor device can prevent exposure of an inner wall of a recess pattern caused by misalignment between masks. A gate electrode is formed inside the recess pattern so that only a gate hard mask layer is exposed above a substrate surface. Since the gate elect... | 12/27/2011 |
| 8084326 | Method for manufacturing semiconductor device The present invention relates to a method for manufacturing a semiconductor device, and provides to reduce a contact resistance of a landing plug by forming the landing plug in such a manner that a polysilicon layer is deposited only on the surface of a landing plug... | 12/27/2011 |
| 8080457 | Fabrication method of power semiconductor structure with low gate charge A fabrication method of a trenched power semiconductor structure with low gate charge is provided. Firstly, a substrate is provided. Then, a gate trench is formed in the substrate. Afterward, a dielectric layer is formed on the inner surfaces of the gate trench. The... | 12/20/2011 |
| 8071445 | Method for manufacturing semiconductor device, and semiconductor device In a transistor region, a source interconnect layer and a gate electrode are buried in trenches. A source extending region is provided adjacent to the transistor region or in the transistor region, and a source interconnect layer is designed to protrude from the upp... | 12/06/2011 |
| 8048739 | Method of manufacturing flash memory device According to yet another embodiment, a method for forming a non-volatile memory device includes etching a substrate to form first and second trenches. The first and second trenches are filled with an insulating material to form first and second isolation structures.... | 11/01/2011 |
| 8043913 | Method of forming trench-gate field effect transistors A method of forming a field effect transistor includes: forming a trench in a semiconductor region; forming a shield electrode in the trench; performing an angled sidewall implant of impurities of the first conductivity type to form a channel enhancement region adja... | 10/25/2011 |
| 8021946 | Nonvolatile memory device and method for fabricating the same A nonvolatile (e.g., flash) memory device includes a substrate having a plurality of isolation areas and active areas; a trench formed on the isolation area; a first electrode layer formed on an inner wall of the trench; a first gate oxide layer formed between the i... | 09/20/2011 |
| 8017479 | Semiconductor device having multi-channel and method of fabricating the same An embodiment of the present invention relates to a semiconductor device having a multi-channel and a method of fabricating the same. In an aspect, the semiconductor device includes a semiconductor substrate in which isolation layers are formed, a plurality of trenc... | 09/13/2011 |
| 8012828 | Recess gate transistor A recess gate of a semiconductor device is provided, comprising: a substrate having a recess formed therein; a metal layer formed at the bottom of the recess; a polysilicon layer formed over the metal layer; and a source region and a drain region formed adjacent to ... | 09/06/2011 |
| 8012829 | Semiconductor device and method of manufacturing the same Example embodiments are directed to a method of manufacturing a semiconductor device and a semiconductor device including a substrate including a plurality of active regions and a plurality of isolation regions between adjacent active regions, each active region inc... | 09/06/2011 |
| 8008151 | Shallow source MOSFET A method of fabricating a semiconductor device comprises forming a hard mask on a substrate having a top substrate surface, forming a trench in the substrate, through the hard mask, depositing gate material in the trench, where the amount of gate material deposited ... | 08/30/2011 |
| 7977189 | Semiconductor device and method of manufacturing the same The present invention relates to a semiconductor device that includes a semiconductor substrate (10) having source/drain diffusion regions (14) formed therein and control gates (20) formed thereon, with grooves (18) being formed on the su... | 07/12/2011 |
| 7977188 | Method for fabricating semiconductor memory device A method for manufacturing a semiconductor device comprises forming a first spacer layer at sidewalls of one or more gate electrodes, forming a trench by etching an isolation insulating layer exposed between the gate electrodes, forming a second spacer layer on side... | 07/12/2011 |
| 7977187 | Method of fabricating a buried-gate semiconductor device and corresponding integrated circuit A semiconductor device includes a semiconductive channel region and a gate region. The gate region has at least one buried part extending under the channel region. The buried part of the gate region is formed by forming a cavity under the channel region. That cavity... | 07/12/2011 |
| 7960229 | Metal oxide semiconductor transistor with reduced gate height, and related fabrication methods A metal oxide semiconductor transistor device having a reduced gate height is provided. One embodiment of the device includes a substrate having a layer of semiconductor material, a gate structure overlying the layer of semiconductor material, and source/drain reces... | 06/14/2011 |
| 7951673 | Forming abrupt source drain metal gate transistors A gate structure may be utilized as a mask to form source and drain regions. Then the gate structure may be removed to form a gap and spacers may be formed in the gap to define a trench. In the process of forming a trench into the substrate, a portion of the source ... | 05/31/2011 |
| 7943463 | Methods of semiconductor processing involving forming doped polysilicon on undoped polysilicon A number of methods are provided for semiconductor processing. One such method includes depositing a first precursor material on a surface at a particular temperature to form an undoped polysilicon. The method also includes depositing a second precursor material on ... | 05/17/2011 |
| 7939409 | Peripheral gate stacks and recessed array gates Methods are provided for simultaneously processing transistors in two different regions of an integrated circuit. Planar transistors are provided in a logic region while recessed access devices (RADs) are provided in an array region for a memory device. During gate ... | 05/10/2011 |
| 7932148 | Processes for manufacturing MOSFET devices with excessive round-hole shielded gate trench (SGT) This invention discloses an improved trenched metal oxide semiconductor field effect transistor (MOSFET) device that includes a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate.... | 04/26/2011 |
| 7923326 | Memory device and method for manufacturing the same A split gate (flash) EEPROM cell and a method for manufacturing the same is disclosed, in which a control gate and a floating gate are formed in a vertical structure, to minimize a size of the cell, to obtain a high coupling ratio, and to lower a programming voltage... | 04/12/2011 |
| 7915121 | Method for manufacturing semiconductor device having buried gate A method for manufacturing a semiconductor device having a buried gate is provided. A gate conductive layer is first formed in the peri region before a bit line contact is formed in the cell region, so that a fabrication process is simplified and the problem caused ... | 03/29/2011 |
| 7906397 | Methods of fabricating nonvolatile semiconductor memory devices including a plurality of stripes having impurity layers therein A nonvolatile semiconductor memory device includes a plurality of pillars protruding upward from a semiconductor substrate and having respective top surfaces and opposing sidewalls, a bit line on the top surfaces of the pillars and connecting a row of the pillars al... | 03/15/2011 |
| 7888206 | Method for manufacturing semiconductor device A method for manufacturing a semiconductor device includes forming a recess with a device separating film and a first hard mask layer so that a pad nitride film for defining a recess gate region may remain with a conventional mask. The method additionally the recess... | 02/15/2011 |
| 7883966 | Memory device and method for manufacturing the same A split gate (flash) EEPROM cell and a method for manufacturing the same is disclosed, in which a control gate and a floating gate are formed in a vertical structure, to minimize a size of the cell, to obtain a high coupling ratio, and to lower a programming voltage... | 02/08/2011 |
| 7883965 | Semiconductor device and method for fabricating the same A semiconductor device includes a device isolation structure, a recess channel structure, and a gate electrode. The device isolation structure is formed in a semiconductor substrate to define an active region. The recess channel structure is disposed in the semicond... | 02/08/2011 |
| 7867846 | Organic light emitting display (OLED) having a gas vent groove to decrease edge open failures An Organic Light Emitting Display (OLED) and its fabrication method has a pixel defining layer provided on a first electrode which is formed with a gas vent groove to allow gas to vent when the pixel defining layer is being formed, so that gas is not left in a pixel... | 01/11/2011 |
| 7867845 | Transistor gate forming methods and transistor structures A transistor gate forming method includes forming a metal layer within a line opening and forming a fill layer within the opening over the metal layer. The fill layer is substantially selectively etchable with respect to the metal layer. A transistor structure inclu... | 01/11/2011 |