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| Number | Title | Issue Date |
| 8187935 | Method of forming active region structure A method of forming an active region structure includes preparing a semiconductor substrate having a cell array region and a peripheral circuit region, forming upper cell mask patterns having a line shape in the cell array region, forming first and second peripheral... | 05/29/2012 |
| 8173505 | Method of making a split gate memory cell A method includes forming a first layer of gate material over a semiconductor substrate; forming a hard mask layer over the first layer; forming an opening; forming a charge storage layer over the hard mask layer and within the opening; forming a second layer of gat... | 05/08/2012 |
| 8163616 | Methods of manufacturing nonvolatile memory devices Nonvolatile memory devices and methods of manufacturing nonvolatile memory devices are provided. The method includes patterning a bulk substrate to form an active pillar; forming a charge storage layer on a side surface of active pillar; and forming a plurality of g... | 04/24/2012 |
| 8138043 | Non-volatile semiconductor memory device and method of manufacturing the same A method of manufacturing a non-volatile semiconductor memory device including previously forming a recess in a first peripheral region on a semiconductor substrate, forming a first gate insulator having a first thickness in the recess, forming a second gate insulat... | 03/20/2012 |
| 8119481 | High-κ capped blocking dielectric bandgap engineered SONOS and MONOS A blocking dielectric engineered, charge trapping memory cell includes a charge trapping element that is separated from a gate by a blocking dielectric including a buffer layer in contact with the charge trapping element, such as silicon dioxide which can be made wi... | 02/21/2012 |
| 8114739 | Semiconductor device with oxygen-diffusion barrier layer and method for fabricating same Methods are provided for fabricating a transistor. An exemplary method involves depositing an oxide layer overlying a layer of semiconductor material, forming an oxygen-diffusion barrier layer overlying the oxide layer, forming a layer of high-k dielectric material ... | 02/14/2012 |
| 8101483 | Semiconductor device and method for manufacturing the same A semiconductor device includes an insulating layer, a channel structure, an insulating structure and a gate. The channel structure includes a channel bridge for connecting two platforms. The bottom of the channel bridge is separated from the insulating layer by a d... | 01/24/2012 |
| 8076199 | Method and device employing polysilicon scaling A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the co... | 12/13/2011 |
| 8067284 | Oxynitride bilayer formed using a precursor inducing a high charge trap density in a top layer of the bilayer A semiconductor device including a bilayer charge storing layer and methods of forming the same are provided. Generally, the method includes: (i) forming a first layer of the bilayer charge storing layer; and (ii) forming a second layer formed on a surface of the fi... | 11/29/2011 |
| 8062945 | Methods of forming non-volatile memory structure with crested barrier tunnel layer Embodiments of methods of forming non-volatile memory structures are provided. In one such embodiment, first and second source/drain regions are formed on a substrate so that the first and second source/drain regions define an intervening channel region. A charge bl... | 11/22/2011 |
| 8017478 | Semiconductor device and method for manufacturing the same A semiconductor device includes a memory cell gate structure having a first gate insulating film, a first gate electrode, a second gate insulating film, and a second gate electrode, a select gate structure having a third gate insulating film and a third gate electro... | 09/13/2011 |
| 8012827 | Method for fabricating a dual workfunction semiconductor device and the device made thereof A method for manufacturing a dual workfunction semiconductor device and the device made thereof are disclosed. In one aspect, the method includes manufacturing a first transistor in a first region and a second transistor in a second region of a substrate, the first ... | 09/06/2011 |
| 8008150 | Methods of fabricating flash memory devices including substantially uniform tunnel oxide layers A method of forming a flash memory device in a memory cell region of a substrate includes forming a first insulating layer on the substrate, forming a first conductive layer on the first insulating layer, forming trench isolation regions in the substrate extending t... | 08/30/2011 |
| 7998812 | Semiconductor device A semiconductor device includes a memory cell array area, a peripheral circuit area on a periphery of the memory cell array area, and a boundary area having a specific width between the memory cell array area and the peripheral circuit area, the memory cell array ar... | 08/16/2011 |
| 7998813 | Methods of fabricating an access transistor having a polysilicon-comprising plug on individual of opposing sides of gate material Fabrication methods for gate transistors in integrated circuit devices enable the formation of recessed access device structures or FinFET structures having P-type workfunctions. The fabrication methods also provide for the formation of access transistor gates of an... | 08/16/2011 |
| 7981744 | Field-effect transistor, semiconductor device, a method for manufacturing them, and a method of semiconductor crystal growth A field-effect transistor which comprises a buffer layer and a barrier layer each of which is made of a Group III nitride compound semiconductor and has a channel at the interface inside of the buffer layer to the barrier layer, wherein the barrier layer has multipl... | 07/19/2011 |
| 7972925 | Flash memory device and fabrication method thereof The present invention relates to a flash memory device and a fabrication method thereof. A trench may be formed within a junction region between word lines by etching a semiconductor substrate between not only a word line and a select line, but also between adjacent... | 07/05/2011 |
| 7932147 | Flash memory device and manufacturing method of the same A flash memory device may include a device isolation layer and an active area formed over a semiconductor substrate, a memory gate formed over the active area, and a control gate formed over the semiconductor substrate including the memory gate, wherein the active a... | 04/26/2011 |
| 7927950 | Method of fabricating trap type nonvolatile memory device A method of fabricating a floating trap type nonvolatile memory device includes forming a cell gate insulating layer on a semiconductor substrate, the cell gate insulating layer being comprised of a lower insulating layer, a charge storage layer and an upper insulat... | 04/19/2011 |
| 7910435 | Method of manufacturing a semiconductor device having a channel extending vertically In a semiconductor device and a method of manufacturing the semiconductor device, the semiconductor device includes a conductive structure, first insulating layers and first conductive layer patterns. The conductive structure includes a first portion, second portion... | 03/22/2011 |
| 7906396 | Flash memory and method of fabricating the same In a method of fabricating a flash memory, a substrate with isolation structures formed therein and a dielectric layer and a floating gate formed thereon between isolation structures is provided. A mask layer is formed on the substrate, covering the isolation struct... | 03/15/2011 |
| 7897457 | Method for manufacturing a nonvolatile semiconductor memory device Bit line diffusion layers are formed in an upper part of a semiconductor substrate with a bit line contact region being interposed between the bit line diffusion layers. A conductive film is formed over the semiconductor substrate, the bit line diffusion layers, and... | 03/01/2011 |
| 7897456 | Non-volatile memory device and method for fabricating the same A non-volatile memory device includes a peripheral circuit region and a cell region. A method for fabricating the non-volatile memory device includes forming gate patterns over a substrate, the gate pattern including a tunnel insulation layer, a floating gate electr... | 03/01/2011 |
| 7888205 | Highly scalable thin film transistor Shrinking the dimensions of PMOS or NMOS thin film transistors is limited by dopant diffusion. In these devices an undoped or lightly doped channel region is interposed between heavily doped source and drain regions. When the device is built with very short gate len... | 02/15/2011 |
| 7883964 | Nonvolatile semiconductor memory and a fabrication method thereof A nonvolatile semiconductor memory includes: a device region and a device isolating region, which have a pattern with a striped form that extends in a first direction, and are alternately and sequentially disposed at a first pitch in a second direction that is perpe... | 02/08/2011 |
| 7867844 | Methods of forming NAND cell units Some embodiments include methods of forming charge storage transistor gates and standard FET gates in which common processing is utilized for fabrication of at least some portions of the different types of gates. FET and charge storage transistor gate stacks may be ... | 01/11/2011 |
| 7863135 | Method of manufacturing a nonvolatile semiconductor memory device, and a nonvolatile semiconductor memory device For enhancing the high performance of a non-volatile semiconductor memory device having an MONOS type transistor, a non-volatile semiconductor memory device is provided with MONOS type transistors having improved performance in which the memory cell of an MONOS non-... | 01/04/2011 |
| 7858472 | Scalable self-aligned dual floating gate memory cell array and methods of forming the array An integrated non-volatile memory circuit is formed by first growing a thin dielectric layer on a semiconductor substrate surface, followed by depositing a layer of conductive material such as doped polysilicon on this dielectric layer, the conductive material then ... | 12/28/2010 |
| 7858471 | Methods of fabricating an access transistor for an integrated circuit device, methods of fabricating periphery transistors and access transistors, and methods of fabricating an access device comprising access transistors in an access circuitry region and peripheral transistors in a peripheral circuitry region spaced from the access circuitry region Fabrication methods for gate transistors in integrated circuit devices enable the formation of recessed access device structures or FinFET structures having P-type workfunctions. The fabrication methods also provide for the formation of access transistor gates of an... | 12/28/2010 |
| 7851307 | Method of forming complex oxide nanodots for a charge trap Methods and devices are disclosed, such as those involving forming a charge trap for, e.g., a memory device, which can include flash memory cells. A substrate is exposed to temporally-separated pulses of a titanium source material, a strontium source material, and a... | 12/14/2010 |
| 7842571 | Method for forming semiconductor device In one embodiment a semiconductor device includes odd contacts and respective odd lines. Spacers are formed on sidewalls of the odd lines and even openings for even lines are formed by performing an etching process. Even contacts are formed in the even openings and ... | 11/30/2010 |
| 7833859 | Method for simultaneously manufacturing semiconductor devices Methods for manufacturing semiconductor devices simultaneously to implement low-voltage and high-voltage devices in a single chip. In one example embodiment, a method includes various acts. An isolation layer is formed on a wafer. A gate oxide layer and a lower gate... | 11/16/2010 |
| 7811885 | Method for forming a phase change device A phase change device may be formed by forming a phase change material and an electrode in a pore in an insulator. The phase change material fills less of the pore than the electrode. ... | 10/12/2010 |
| 7772067 | Methods of forming phase-changeable memory devices using growth-enhancing and growth-inhibiting layers for phase-changeable materials Methods of forming phase-changeable memory devices include techniques to inhibit void formation in phase-changeable materials in order to increase device reliability. These techniques to inhibit void formation use an electrically insulating growth-inhibiting layer t... | 08/10/2010 |
| 7767523 | Semiconductor device with integrated flash memory and peripheral circuit and its manufacture method A non-volatile semiconductor memory device includes: a nonvolatile memory area including gate electrodes, each including stack of a floating gate, an inter-electrode insulating film and a control gate, and having first insulating side walls formed on side walls of t... | 08/03/2010 |
| 7759195 | Semiconductor device including transistor with composite gate structure and transistor with single gate structure, and method for manufacturing the same A semiconductor device comprises a first transistor having a composite gate structure containing a lamination of a first polycrystalline silicon film, an interlayer insulating film, and a second polycrystalline silicon film; and a second transistor having a single g... | 07/20/2010 |
| 7759194 | Electrically programmable device with embedded EEPROM and method for making thereof An electrically programmable device with embedded EEPROM and method for making thereof. The method includes providing a substrate including a first device region and a second device region, growing a first gate oxide layer in the first device region and the second d... | 07/20/2010 |
| 7749836 | Nonvolatile semiconductor memory and manufacturing method thereof A method for manufacturing a nonvolatile semiconductor memory device including: forming a first and a second stacked gate structures, each of which including a first polysilicon layer formed on a silicon substrate via a gate insulator, an inter-gate insulator formed... | 07/06/2010 |
| 7727839 | Method of manufacturing NAND flash memory device A method of manufacturing a NAND flash memory device is disclosed. A semiconductor substrate of a portion in which a source select line SSL and a drain select line DSL will be formed is recessed selectively or entirely to a predetermined depth. Accordingly, the chan... | 06/01/2010 |
| 7727840 | Forming integrated circuit devices Methods of forming integrated circuit devices are provided. A first mask layer is formed overlying a first portion of a semiconductor substrate. The first mask layer further overlies a second mask layer overlying a second portion of the semiconductor substrate. The ... | 06/01/2010 |
