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| Number | Title | Issue Date |
| 8071442 | Transistor with embedded Si/Ge material having reduced offset to the channel region A strain-inducing semiconductor alloy may be formed on the basis of cavities which may have a non-rectangular shape, which may be maintained even during corresponding high temperature treatments by providing an appropriate protection layer, such as a silicon dioxide... | 12/06/2011 |
| 8030158 | Method for fabricating contacts in semiconductor device Disclosed is a method for fabricating a contact in a semiconductor device, including: obtaining a pattern layout including bit lines arranged across a cell matrix region of a semiconductor substrate, cell storage node contacts arranged to pass through a portion of a... | 10/04/2011 |
| 8017476 | Method for manufacturing a junction field effect transistor having a double gate A junction field effect transistor includes a channel region, a gate region coupled to the channel region, a well tap region coupled to the gate region and the channel region, and a well region coupled to the well tap region and the channel region. A double gate ope... | 09/13/2011 |
| 7989287 | Method for fabricating storage node electrode in semiconductor device A method for fabricating a storage node electrode in a semiconductor device includes: performing a primary high density plasma (HDP) process to form a first HDP oxide film over an etch stop film; performing a secondary HDP process to form a second HDP oxide film on ... | 08/02/2011 |
| 7960228 | Methods of making a ferroelectric memory device having improved interfacial characteristics The present invention provides a method for manufacturing a semiconductor device, including the steps of: forming a first ferroelectric film on a first conductive film by a film-forming method including at least a step of forming a film by a sol-gel method; forming ... | 06/14/2011 |
| 7939405 | Method of manufacturing semiconductor device having cylinder-type capacitor structure A method of manufacturing a semiconductor device includes forming an inter-layer insulating film; arranging a plurality of grooves in a surface layer of the inter-layer insulating film; forming embedded insulating films which are embedded in the grooves; arranging a... | 05/10/2011 |
| 7772065 | Semiconductor memory device including a contact with different upper and bottom surface diameters and manufacturing method thereof A semiconductor memory device includes diffusion regions formed in an active region; cell contacts connected to the diffusion regions, respectively; pillars connected to the cell contacts, respectively; a bit line connected to the pillar; capacitor contacts connecte... | 08/10/2010 |
| 7723183 | Capacitor having tapered cylindrical storage node and method for manufacturing the same A capacitor is made by forming a buffer oxide layer, an etching stop layer, and a mold insulation layer over a semiconductor substrate having a storage node contact plug. The mold insulation layer and the etching stop layer are etched to form a hole in an upper port... | 05/25/2010 |
| 7659164 | Method for fabricating capacitor of semiconductor device A method for fabricating a capacitor of a semiconductor device comprises forming a silicon nanowire structure having a large aspect ratio using a porous anodic alumina structure and applying the silicon nanowire structure to a bottom electrode, thereby obtaining a c... | 02/09/2010 |
| 7629218 | Method of manufacturing a capacitor and method of manufacturing a semiconductor device using the same Example embodiments relate to a method of manufacturing a capacitor and a method of manufacturing a semiconductor device using the same. Other example embodiments relate to a method of manufacturing a capacitor having improved characteristics and a method of manufac... | 12/08/2009 |
| 7452770 | Reduced cell-to-cell shorting for memory arrays Bottom electrodes of memory cell capacitors are recessed to prevent electrical shorts between neighboring memory cells. A partially fabricated memory cell capacitor has a bottom electrode comprising titanium nitride (TiN) and hemispherical grained (HSG) silicon. The... | 11/18/2008 |
| 7402466 | Strained silicon CMOS on hybrid crystal orientations Methods of forming a strained Si-containing hybrid substrate are provided as well as the strained Si-containing hybrid substrate formed by the methods. In the methods of the present invention, a strained Si layer is formed overlying a regrown semiconductor material,... | 07/22/2008 |
| 7399671 | Disposable pillars for contact formation Sacrificial plugs for forming contacts in integrated circuits, as well as methods of forming connections in integrated circuit arrays are disclosed. Various pattern transfer and etching steps can be used to create densely-packed features and the connections between ... | 07/15/2008 |
| 7393742 | Semiconductor device having a capacitor and a fabrication method thereof In a semiconductor device having a capacitor and a method of fabricating the same, the semiconductor device comprises a semiconductor substrate and an insulating layer on the semiconductor substrate, a contact plug electrically connected to the semiconductor substra... | 07/01/2008 |
| 7374992 | Manufacturing method for an integrated semiconductor structure The present invention provides a manufacturing method for an integrated semiconductor structure comprising the steps of: providing a semiconductor substrate having a plurality of gate stacks in a memory cell region and at least one gate stack in a peripheral device ... | 05/20/2008 |
| 7364966 | Method for forming a buried digit line with self aligning spacing layer and contact plugs during the formation of a semiconductor device, semiconductor devices, and systems including same A method for use during fabrication of a semiconductor device comprises the formation of buried digit lines and contacts. During formation, a buried bit line layer may be used as a mask to etch one or more openings in a dielectric layer. A conductive layer is then f... | 04/29/2008 |
| 7364996 | Methods of fabricating patterned layers on a substrate A method of fabricating a pattern on a substrate, comprises the steps of: depositing; such as by ink-jet printing, multiple drops of a first liquid material as a first deposit (15) on the substrate: depositing, such as by ink-jet printing, multiple drops of a... | 04/29/2008 |
| 7352034 | Semiconductor structures integrating damascene-body FinFET's and planar devices on a common substrate and methods for forming such semiconductor structures Methods of forming a semiconductor structure having FinFET's and planar devices, such as MOSFET's, on a common substrate by a damascene approach. A semiconductor fin of the FinFET is formed on a substrate with damascene processing in which the fin growth may be inte... | 04/01/2008 |
| 7348238 | Bottom electrode for memory device and method of forming the same Contacts having use in an integrated circuit and exemplary methods of forming the contacts are disclosed. The methods involve forming a conductive cap over a metal plug. The invention can mitigate keyholes in the contacts by capping and encapsulating the conductive ... | 03/25/2008 |
| 7341956 | Disposable hard mask for forming bit lines A method includes forming a group of disposable hard mask structures on a semiconductor device that includes a group of memory cells. The method further includes using the disposable hard mask structures to precisely control a junction profile of the memory cells. | 03/11/2008 |
| 7338610 | Etching method for manufacturing semiconductor device A wafer having a dielectric layer and an electrode partially protruding from the top surface of the dielectric layer is provided. The dielectric layer is etched with a chemical solution such as LAL. Prior to etching, the protruding portion of the electrode is remove... | 03/04/2008 |
| 7335589 | Method of forming contact via through multiple layers of dielectric material In a manufacture of a semiconductor device, spacers are formed on sidewalls of structures including conductive patterns and insulation patterns. The insulation patterns are at least four times thinner than the conductive patterns. After gaps between the structures a... | 02/26/2008 |
| 7332389 | Selective polysilicon stud growth A memory cell having a bit line contact is provided. The memory cell may be a 6F2 memory cell. The bit line contact may have a contact hole bounded by insulating sidewalls, and the contact hole may be partially or completely filled with a doped polysilico... | 02/19/2008 |
| 7329569 | Methods of forming semiconductor devices including mesa structures and multiple passivation layers A method of forming a semiconductor device may include forming a semiconductor structure on a substrate wherein the semiconductor structure defines a mesa having a mesa surface opposite the substrate and mesa sidewalls between the mesa surface and the substrate. A f... | 02/12/2008 |
| 7326613 | Methods of manufacturing semiconductor devices having elongated contact plugs A method of manufacturing a semiconductor device includes forming conductive structures on a substrate. Each of the conductive structures has a line shape that extends along a first direction parallel to the substrate. Insulating spacers are formed on upper sidewall... | 02/05/2008 |
| 7323710 | Fin field effect transistors having multi-layer fin patterns A fin field effect transistor has a fin pattern protruding from a semiconductor substrate. The fin pattern includes first semiconductor patterns and second semiconductor patterns which are stacked. The first and second semiconductor patterns have lattice widths that... | 01/29/2008 |
| 7319057 | Phase change material memory device A lower electrode may be covered by a protective film to reduce the exposure of the lower electrode to subsequent processing steps or the open environment. As a result, materials that may have advantageous properties as lower electrodes may be utilized despite the f... | 01/15/2008 |
| 7316954 | Methods of fabricating integrated circuit devices that utilize doped poly-SiGeconductive plugs as interconnects The present invention provides integrated circuit devices that include a semiconductor substrate having a semiconductor region of first conductivity type therein extending adjacent the surface of the substrate. The device further includes an electrically insulating ... | 01/08/2008 |
| 7314800 | Application of different isolation schemes for logic and embedded memory The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relat... | 01/01/2008 |
| 7312121 | Method of manufacturing a semiconductor memory device Manufacturing a semiconductor memory by first forming a first insulating layer covering a conductive pad. Next forming and pattering a bit line conductive layer and a second insulating layer to expose a part of the first insulating layer. A third insulating layer co... | 12/25/2007 |
| 7303939 | Electro- and electroless plating of metal in the manufacture of PCRAM devices Non-volatile, resistance variable memory devices, integrated circuit elements, and methods of forming such devices are provided. According to one embodiment of a method of the invention, a memory device can be fabricated by depositing a chalcogenide material onto a ... | 12/04/2007 |
| 7300839 | Selective polysilicon stud growth A memory cell having a bit line contact is provided. The memory cell may be a 6F2 memory cell. The bit line contact may have a contact hole bounded by insulating sidewalls, and the contact hole may be partially or completely filled with a doped polysilico... | 11/27/2007 |
| 7294545 | Selective polysilicon stud growth A memory cell having a bit line contact is provided. The memory cell may be a 6F2 memory cell. The bit line contact may have a contact hole bounded by insulating sidewalls, and the contact hole may be partially or completely filled with a doped polysilico... | 11/13/2007 |
| 7291532 | Low resistance contact in a semiconductor device In a method for manufacturing a contact electrically contacting an electrically conductive silicon structure, a substrate with a surface is provided, the substrate having the silicon structure at the surface. Silicon oxide is grown selectively on at least part of th... | 11/06/2007 |
| 7282406 | Method of forming an MOS transistor and structure therefor In one embodiment, an MOS transistor is formed with trench gates. The gate structure of the trench gates generally has a first insulator that has a first thickness in one region of the gate and a second thickness in a second region of the gate. ... | 10/16/2007 |
| 7282387 | Electro- and electroless plating of metal in the manufacture of PCRAM devices Non-volatile, resistance variable memory devices, integrated circuit elements, and methods of forming such devices are provided. According to one embodiment of a method of the invention, a memory device can be fabricated by depositing a chalcogenide material onto a ... | 10/16/2007 |
| 7279754 | Semiconductor memory device and a method of manufacturing the same A memory cell of a SRAM has two drive MISFETs and two vertical MISFETs. The p channel vertical MISFETs are formed above the n channel drive MISFETs. The vertical MISFETs respectively mainly consist of a square pole laminate formed of a lower semiconductor layer, int... | 10/09/2007 |
| 7265405 | Method for fabricating contacts for integrated circuits, and semiconductor component having such contacts One (or more) contacts are produced on one or more active areas of a semiconductor wafer, it being possible for one or more isolated control lines to be arranged on the active areas with which contact is to be made. The control lines may, for example, be gate lines.... | 09/04/2007 |
| 7264988 | Electro-and electroless plating of metal in the manufacture of PCRAM devices Non-volatile, resistance variable memory devices, integrated circuit elements, and methods of forming such devices are provided. According to one embodiment of a method of the invention, a memory device can be fabricated by depositing a chalcogenide material onto a ... | 09/04/2007 |
| 7259055 | Method of forming high-luminescence silicon electroluminescence device A method for forming a high-luminescence Si electroluminescence (EL) phosphor is provided, with an EL device made from the Si phosphor. The method comprises: depositing a silicon-rich oxide (SRO) film, with Si nanocrystals, having a refractive index in the range of ... | 08/21/2007 |
