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| Number | Title | Issue Date |
| 7759190 | Memory device and fabrication method thereof A fabrication method of a memory device is disclosed. A substrate having a trench is provided, comprising a trench capacitor, a conductive column, a collar dielectric layer and a top dielectric layer therein. A gate structure with spacers on sidewalls is disposed on... | 07/20/2010 |
| 7470585 | Integrated circuit and fabrication process An integrated circuit has at least one semiconductor device for storing charge that includes at least one elementary active component and at least one elementary storage capacitor. The device includes a substrate having a lower region containing at least one buried ... | 12/30/2008 |
| 7410864 | Trench and a trench capacitor and method for forming the same A method for fabricating a trench includes providing a semiconductor substrate made of a semiconductor material. A trench is etched into a surface of the semiconductor substrate such that a trench wall is produced. At least one layer is provided on the trench wall. ... | 08/12/2008 |
| 7402487 | Process for fabricating a semiconductor device having deep trench structures A process for fabricating a semiconductor device having deep trench structures includes forming a first portion of the trench in a semiconductor substrate and a second portion of the trench in a selectively-formed upper layer. After etching the substrate to form the... | 07/22/2008 |
| 7390717 | Trench power MOSFET fabrication using inside/outside spacers A fabrication process for a trench type power semiconductor device includes forming inside spacers over a semiconductor surface. Using the spacers as masks, trenches with gates are formed in the semiconductor body. After removing the spacers, source implants are for... | 06/24/2008 |
| 7332395 | Method of manufacturing a capacitor A method of manufacturing a stack capacitance type capacitor is provided, which prevents the problem that the capacitor cannot be formed because a lower electrode collapses with the external wall thereof exposed in forming the lower electrode of the capacitor in a d... | 02/19/2008 |
| 7323424 | Semiconductor constructions comprising cerium oxide and titanium oxide The invention includes semiconductor constructions comprising dielectric materials which contain cerium oxide and titanium oxide. The dielectric materials can contain a homogeneous distribution of cerium oxide and titanium oxide, and/or can contain a laminate of cer... | 01/29/2008 |
| 7320912 | Trench capacitors with buried isolation layer formed by an oxidation process and methods for manufacturing the same A method for forming a trench capacitor includes: removing a portion of the substrate to form a trench within the substrate; forming at a buried isolation layer within the substrate; forming in the substrate a first electrode of the trench capacitor at least in area... | 01/22/2008 |
| 7301200 | Trench FET with self aligned source and contact A trench type power MOSgated device has a plurality of spaced trenches lined with oxide and filled with conductive polysilicon. The tops of the polysilicon fillers are below the top silicon surface and are capped with a deposited oxide the top of which is flush with... | 11/27/2007 |
| 7271052 | Long retention time single transistor vertical memory gain cell A single transistor vertical memory gain cell with long data retention times. The memory cell is formed from a silicon carbide substrate to take advantage of the higher band gap energy of silicon carbide as compared to silicon. The silicon carbide provides much lowe... | 09/18/2007 |
| 7241659 | Volatile memory devices and methods for forming same A method for forming a volatile memory device. A substrate comprising a pair of neighboring trenches is provided, each trench comprising a capacitor. A collar insulating layer is formed on an upper sidewall of each trench. The collar insulating layer comprises a low... | 07/10/2007 |
| 7229877 | Trench capacitor with hybrid surface orientation substrate Methods of forming a deep trench capacitor memory device and logic devices on a single chip with hybrid surface orientation. The methods allow for fabrication of a system-on-chip (SoC) with enhanced performance including n-type complementary metal oxide semiconducto... | 06/12/2007 |
| 7223651 | Dram memory cell with a trench capacitor and method for production thereof A memory cell includes a selection transistor and a trench capacitor. The trench capacitor is filled with a conductive trench filling on which an insulating covering layer is arranged. The insulating covering layer is laterally overgrown, proceeding from the substra... | 05/29/2007 |
| 7220640 | Method of fabricating recess transistor in integrated circuit device and recess transistor in integrated circuit device fabricated by the same Provided is a method of fabricating a recess transistor in an integrated circuit device. In the provided method, a device isolation region, which contacts to the sidewall of a gate trench and a substrate region remaining between the sidewall of the device isolation ... | 05/22/2007 |
| 7217633 | Methods for fabricating an STI film of a semiconductor device Methods for fabricating a shallow trench isolation (STI) of a semiconductor device are disclosed. A disclosed method includes: forming a trench on a semiconductor substrate, forming an oxide layer on the semiconductor substrate and the trench, forming a photoresist ... | 05/15/2007 |
| 7205193 | Semiconductor device and method for fabricating the same A semiconductor device and method for fabricating the same. The semiconductor device including a first conductive type semiconductor substrate having an active region and a field region defined thereon, and a trench formed in the field region. The semiconductor devi... | 04/17/2007 |
| 7170126 | Structure of vertical strained silicon devices A trench capacitor vertical-transistor DRAM cell in a SiGe wafer compensates for overhang of the pad nitride by forming an epitaxial strained silicon layer on the trench walls that improves transistor mobility, removes voids from the poly trench fill and reduces res... | 01/30/2007 |
| 7157328 | Selective etching to increase trench surface area The surface area of the walls of a trench formed in a substrate is increased. A barrier layer is formed on the walls of the trench such that the barrier layer is thinner near the corners of the trench and is thicker between the corners of the trench. A dopant is int... | 01/02/2007 |
| 7157329 | Trench capacitor with buried strap A trench capacitor with improved strap is disclosed. The strap is located above the top surface of the capacitor. The top surface of the trench capacitor, which is formed by the top surfaces of the collar and storage plate, is planar. By locating the strap on a plan... | 01/02/2007 |
| 7148103 | Multilevel poly-Si tiling for semiconductor circuit manufacture Method of manufacturing a semiconductor device, including a first baseline technology electronic circuit (1) and a second option technology electronic circuit (2) as functional parts of a system-on-chip, by: manufacturing the first electro... | 12/12/2006 |
| 7144770 | Memory cell and method for fabricating it The invention provides a method for fabricating a memory cell, a substrate (101) being provided, a trench-type depression (102) being etched into the substrate (101), a barrier layer (103) being deposited non-conformally in the trench-typ... | 12/05/2006 |
| 7122439 | Method of fabricating a bottle trench and a bottle trench capacitor A method of fabricating a bottle trench and a bottle trench capacitor. The method including: providing a substrate; forming a trench in the substrate, the trench having sidewalls and a bottom, the trench having an upper region adjacent to a top surface of the substr... | 10/17/2006 |
| 7115933 | Integrated circuit and fabrication process An integrated circuit has at least one semiconductor device for storing charge that includes at least one elementary active component and at least one elementary storage capacitor. The device includes a substrate having a lower region containing at least one buried ... | 10/03/2006 |
| 7109543 | Semiconductor device having trench capacitor and method for fabricating the same A semiconductor device and a method for fabricating the same. The device comprises a silicon substrate having a conductive well; a trench formed in the conductive well; a plate electrode formed on the sidewall of the trench; a capacitor insulating film and a storage... | 09/19/2006 |
| 7101768 | Self-aligned selective hemispherical grain deposition process and structure for enhanced capacitance trench capacitor As disclosed herein, a method is provided, in an integrated circuit, for forming an enhanced capacitance trench capacitor. The method includes forming a trench in a semiconductor substrate and forming an isolation collar on a sidewall of the trench. The collar has a... | 09/05/2006 |
| 7101785 | Formation of a contact in a device, and the device including the contact A method of forming a contact to an underlayer of a device includes the steps of forming a contact hole, forming a contact hole barrier layer of a barrier material in the contact hole of the device, etching the contact hole barrier layer on the bottom surface of the... | 09/05/2006 |
| 7098100 | Trench capacitor and method for preparing the same The present invention discloses a trench capacitor formed in a trench in a semiconductor substrate. The trench capacitor comprises a bottom electrode positioned on a lower outer surface of the trench, a dielectric layer positioned on an inner surface of the bottom e... | 08/29/2006 |
| 7098102 | Shallow trench isolation structure and dynamic random access memory, and fabricating methods thereof A method for fabricating a shallow trench isolation (STI) structure is described. A patterned mask layer is formed on a substrate. An ion implantation is performed to form a doped region in a predetermined depth in the substrate exposed by the mask layer. An etching... | 08/29/2006 |
| 7094659 | Method of forming deep trench capacitors A method of forming a trench capacitor is disclosed. After completion of the bottom electrode of the capacitor, a collar dielectric layer is directly formed on the sidewall of the deep trench using self-starved atomic layer chemical vapor deposition (self-starved AL... | 08/22/2006 |
| 7084029 | Method for fabricating a hole trench storage capacitor in a semiconductor substrate, and hole trench storage capacitor To fabricate a hole trench storage capacitor having an inner electrode, which is formed in a hole trench, and an outer electrode, which is formed in an electrode section, surrounding the hole trench in a lower section, of the semiconductor substrate, the inner elect... | 08/01/2006 |
| 7084028 | Semiconductor device and method of manufacturing a semiconductor device A semiconductor device comprises a semiconductor substrate having a cavity region inside; a first insulation film formed on the inner wall of the cavity region; a first electrode formed on the inner wall of the first insulation film in the cavity region, and having ... | 08/01/2006 |
| 7067351 | Selectively-etched nanochannel electrophoretic and electrochemical devices Nanochannel electrophoretic and electrochemical devices having selectively-etched nanolaminates located in the fluid transport channel. The normally flat surfaces of the nanolaminate having exposed conductive (metal) stripes are selectively-etched to form trenches a... | 06/27/2006 |
| 7067372 | Method for fabricating a memory cell having a trench A memory cell has a trench, in which a trench capacitor is disposed. Furthermore a vertical transistor is formed in the trench above the trench capacitor. A barrier layer is disposed for the electric connection of the conductive trench filling to a lower doping regi... | 06/27/2006 |
| 7060596 | Process for fabricating a single-crystal substrate and integrated circuit comprising such a substrate An initial single-crystal substrate 1 having, locally and on the surface, at least one discontinuity in the single-crystal lattice is formed. The initial substrate is recessed at the discontinuity. The single-crystal lattice is amorphized around the periphery... | 06/13/2006 |
| 7052966 | Deep N wells in triple well structures and method for fabricating same A disclosed method for fabricating a structure in a semiconductor die comprises steps of implanting a deep N well in a substrate, depositing an epitaxial layer over the substrate, and forming a P well and a lateral isolation N well over the deep N well, wherein the ... | 05/30/2006 |
| 7045859 | Trench fet with self aligned source and contact A trench type power MOSgated device has a plurality of spaced trenches lined with oxide and filled with conductive polysilicon. The tops of the polysilicon fillers are below the top silicon surface and are capped with a deposited oxide the top of which is flush with... | 05/16/2006 |
| 7041556 | Vertical transistor and method of making The invention relates to a vertical transistor and an oxidation process that achieves a substantially curvilinear recess bottom. The recess serves as the gate receptacle that may facilitate a more uniform gate oxide layer. One embodiment relates to a storage cell th... | 05/09/2006 |
| 7012289 | Memory cell having a thin insulation collar and memory module A memory cell has a trench capacitor, in which the area required over a terminal area of the trench capacitor is advantageously reduced by the formation of a particularly thin insulation collar. The insulation collar is reduced to such an extent that although a late... | 03/14/2006 |
| 7012024 | Methods of forming a transistor with an integrated metal silicide gate electrode Methods of forming a transistor having integrated metal silicide transistor gate electrode on a semiconductor assembly are described. The transistor gate is partially fabricated by reacting the metal with epitaxial silicon while residing in a trench to form metal si... | 03/14/2006 |
| 6998666 | Nitrided STI liner oxide for reduced corner device impact on vertical device performance A method of fabricating an integrated circuit device comprises etching a trench in a substrate and forming a dynamic random access memory (DRAM) cell having a storage capacitor at a lower end and an overlying vertical metal oxide semiconductor field effect transisto... | 02/14/2006 |
