An enclosure for small animals which is wearable on the front or back of an animate being.
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| Number | Title | Issue Date |
| 8178405 | Resistor random access memory cell device A memory cell device has a bottom electrode and a top electrode, a plug of memory material in contact with the bottom electrode, and a cup-shaped conductive member having a rim that contacts the top electrode and an opening in the bottom that contacts the memory mat... | 05/15/2012 |
| 7951665 | Semiconductor device having capacitor formed on plug, and method of forming the same A semiconductor device includes a silicon substrate, a capacitor element having a lower electrode, a capacitor dielectric film, a TiN film, and a W film, and an interlayer insulation film covering the end and a portion of the upper surface of the lower electrode and... | 05/31/2011 |
| 7947553 | Method for fabricating semiconductor device with recess gate A method for fabricating a semiconductor device includes forming a first recess in a substrate, forming a plasma oxide layer over the substrate including first recess, etching the plasma oxide layer to have a portion of the plasma oxide layer remain on sidewalls of ... | 05/24/2011 |
| 7851301 | Semiconductor capacitor structure and method to form same A semiconductor capacitor structure comprising sidewalls of conductive hemispherical grained material, a base of metal silicide material, and a metal nitride material overlying the conductive hemispherical grained material and the metal silicide material. The semico... | 12/14/2010 |
| 7829410 | Methods of forming capacitors, and methods of forming DRAM arrays Some embodiments include methods of forming capacitors. A first section of a capacitor may be formed to include a first storage node, a first dielectric material, and a first plate material. A second section of the capacitor may be formed to include a second storage... | 11/09/2010 |
| 7785961 | Trench DRAM cell with vertical device and buried word lines A DRAM array having trench capacitor cells of potentially 4F2 surface area (F being the photolithographic minimum feature width), and a process for fabricating such an array. The array has a cross-point cell layout in which a memory cell is located at the... | 08/31/2010 |
| 7745281 | Thin solid electrolytic capacitor embeddable in a substrate An improved method for forming a capacitor. The method includes the steps of: providing a metal foil; forming a dielectric on the metal foil; applying a non-conductive polymer dam on the dielectric to isolate discrete regions of the dielectric; forming a cathode in ... | 06/29/2010 |
| 7713817 | Methods of forming semiconductor structures Electroless plating can be utilized to form electrical interconnects associated with semiconductor substrates. For instance, a semiconductor substrate can be formed to have a dummy structure thereover with a surface suitable for electroless plating, and to also have... | 05/11/2010 |
| 7713815 | Semiconductor device including a vertical decoupling capacitor A vertical or three-dimensional non-planar configuration for a decoupling capacitor is provided, which significantly reduces the required die area for capacitors of high charge carrier storage capacity. The non-planar configuration of the decoupling capacitors also ... | 05/11/2010 |
| 7713816 | Semiconductor device and method for fabricating the same A method for fabricating a semiconductor device having a capacitor is provided. The method includes forming an isolation layer on a substrate on which a capacitor region and a transistor region are defined, forming a trench in the isolation layer, sequentially formi... | 05/11/2010 |
| 7700436 | Method for forming a microelectronic structure having a conductive material and a fill material with a hardness of 0.04 GPA or higher within an aperture A microelectronic substrate and method for removing adjacent conductive and nonconductive materials from a microelectronic substrate. In one embodiment, the microelectronic substrate includes a substrate material (such as borophosphosilicate glass) having an apertur... | 04/20/2010 |
| 7696042 | Semiconductor capacitor structure and method to form same A semiconductor capacitor structure comprising sidewalls of conductive hemispherical grained material, a base of metal silicide material, and a metal nitride material overlying the conductive hemispherical grained material and the metal silicide material. The semico... | 04/13/2010 |
| 7670902 | Method and structure for landing polysilicon contact A method for fabricating an integrated circuit device. A plurality of MOS transistor devices are formed overlying a semiconductor substrate. Each of the MOS transistor devices includes a nitride cap and nitride sidewall spacers. An interlayer dielectric layer is for... | 03/02/2010 |
| 7651909 | Method for fabricating metal-insulator-metal capacitor A method for fabricating a metal-insulator-metal capacitor is described. A first metal layer is formed on a substrate. A plasma treatment is performed on the surface of the first metal layer. Then, a first oxide layer, a nitride layer and a second oxide layer are fo... | 01/26/2010 |
| 7524724 | Method of forming titanium nitride layer and method of fabricating capacitor using the same A method of fabricating a storage capacitor includes depositing a first titanium nitride layer on a dielectric layer using a chemical vapor deposition technique or an atomic layer deposition technique performed at a first temperature with reactant gases of titanium ... | 04/28/2009 |
| 7504299 | Folded node trench capacitor A trench capacitor is filled with a set of two or more storage plates by consecutively depositing layers of dielectric and conductor and making contact to the ground plates by etching an aperture through the plates to the buried plate in the substrate and connecting... | 03/17/2009 |
| 7449382 | Memory device and fabrication method thereof A memory device is disclosed. A substrate is provided. A plurality of pillars is disposed on the substrate. Each pillar has a plurality of epitaxial layers, has a first sidewall and a second sidewall. A trench is formed between the pillars. A common bottom electrode... | 11/11/2008 |
| 7442602 | Methods of fabricating phase change memory cells having a cell diode and a bottom electrode self-aligned with each other Integrated circuit devices are provided having a vertical diode therein. The devices include an integrated circuit substrate and an insulating layer on the integrated circuit substrate. A contact hole penetrates the insulating layer. A vertical diode is in a lower r... | 10/28/2008 |
| 7439130 | Semiconductor device with capacitor and method for fabricating the same A method of fabricating a semiconductor device having a capacitor is provided. The method includes forming second, third, fourth, and fifth insulating layers on a first conductive layer formed in a first insulating layer. The fourth insulating layer is patterned int... | 10/21/2008 |
| 7429509 | Method for forming a semiconductor device A method for forming a semiconductor device. A substrate is provided, wherein the substrate has recessed gates and deep trench capacitor devices therein. Protrusions of the recessed gates and upper portions of the deep trench capacitor devices are revealed. Spacers ... | 09/30/2008 |
| 7410863 | Methods of forming and using memory cell structures A method of filling vias for a PCRAM cell with a metal is described. A PCRAM intermediate structure including a substrate, a first conductor, and an insulator through which a via extends has a metallic material formed within the via and on a surface of the insulator... | 08/12/2008 |
| 7410864 | Trench and a trench capacitor and method for forming the same A method for fabricating a trench includes providing a semiconductor substrate made of a semiconductor material. A trench is etched into a surface of the semiconductor substrate such that a trench wall is produced. At least one layer is provided on the trench wall. ... | 08/12/2008 |
| 7405133 | Semiconductor device and method for manufacturing the same A semiconductor device comprising a semiconductor substrate, and a plurality of capacitors formed on the semiconductor substrate. The capacitors comprise a plurality of lower electrodes formed on the semiconductor substrate, a ferroelectric film formed continuously ... | 07/29/2008 |
| 7402486 | Cylinder-type capacitor and storage device, and method(s) for fabricating the same A one cylinder storage device and a method for fabricating a capacitor are disclosed, realizing simplified fabrication by overexposure with a mask having a plurality of holes, in which the method includes forming a contact hole in an insulating layer on a semiconduc... | 07/22/2008 |
| 7393741 | Methods of forming pluralities of capacitors The invention comprises methods of forming pluralities of capacitors. In one implementation, metal is formed over individual capacitor storage node locations on a substrate. A patterned masking layer is formed over the metal. The patterned masking layer comprises op... | 07/01/2008 |
| 7393742 | Semiconductor device having a capacitor and a fabrication method thereof In a semiconductor device having a capacitor and a method of fabricating the same, the semiconductor device comprises a semiconductor substrate and an insulating layer on the semiconductor substrate, a contact plug electrically connected to the semiconductor substra... | 07/01/2008 |
| 7390717 | Trench power MOSFET fabrication using inside/outside spacers A fabrication process for a trench type power semiconductor device includes forming inside spacers over a semiconductor surface. Using the spacers as masks, trenches with gates are formed in the semiconductor body. After removing the spacers, source implants are for... | 06/24/2008 |
| 7390730 | Method of fabricating a body capacitor for SOI memory A semiconductor structure having a body capacitance plate, which is formed with a process that assures that the body capacitance plate is self-aligned to both the source line (SL) diffusion and the bitline diffusion is provided. Thus the amount of overlap between th... | 06/24/2008 |
| 7384852 | Sub-lithographic gate length transistor using self-assembling polymers A semiconductor structure including at least one transistor located on a surface of a semiconductor substrate, wherein the at least one transistor has a sub-lithographic channel length, is provided. Also provided is a method to form such a semiconductor structure us... | 06/10/2008 |
| 7371645 | Method of manufacturing a field effect transistor device with recessed channel and corner gate device Fabrication of recessed channel array transistors (RCAT) with a corner gate device includes forming pockets between a semiconductor fin that includes a gate groove and neighboring shallow trench isolations that extend along longs sides of the semiconductor fin. A pr... | 05/13/2008 |
| 7371589 | Ferroelectric random access memory capacitor and method for manufacturing the same The method for manufacturing an FeRAM capacitor with a merged top electrode plate line (MTP) structure is employed to prevent a detrimental impact on the FeRAM and to secure a reliable FeRAM device. The method includes steps of: preparing an active matrix obtained b... | 05/13/2008 |
| 7372113 | Semiconductor device and method of manufacturing the same Disclosed is a semiconductor device comprising a semiconductor substrate, a gate electrode, a first insulating film formed between the semiconductor substrate and the gate electrode, and a second insulating film formed along a top surface or a side surface of the ga... | 05/13/2008 |
| 7364963 | Method for fabricating semiconductor device A method for fabricating a semiconductor device is provided. The method includes: implanting impurities onto a substrate by performing an ion implantation process; recessing portions of the substrate to form a plurality of trenches; performing a first thermal proces... | 04/29/2008 |
| 7358556 | SRAM cell structure and manufacturing method thereof A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an openi... | 04/15/2008 |
| 7354823 | Methods of forming integrated circuit devices having carbon nanotube electrodes therein An integrated circuit capacitor includes first and second electrodes and at least one dielectric layer extending between the first and second electrodes. The first electrode includes at least one carbon nanotube. The capacitor further includes an electrically conduc... | 04/08/2008 |
| 7354822 | Method of forming a MOSFET with dual work function materials A vertical pass transistor used in a DRAM cell for maintaining a low total leakage current and providing adequate drive current is described together with a method of fabricating such a device. The transistor gate is engineered in lieu of the channel. The vertical p... | 04/08/2008 |
| 7355230 | Transistor array for semiconductor memory devices and method for fabricating a vertical channel transistor array A transistor array for semiconductor memory devices is provided. A plurality of semiconductor pillars extending outwardly from a bulk section of a semiconductor substrate is arranged in rows and columns. Each pillar forms an active area of a vertical channel access ... | 04/08/2008 |
| 7354821 | Methods of fabricating trench capacitors with insulating layer collars in undercut regions Trench capacitors that have insulating layer collars in undercut regions and methods of fabricating such trench capacitors are provided. Some methods of fabricating a trench capacitor include forming a first layer on a substrate. A second layer is formed on the firs... | 04/08/2008 |
| 7341901 | Semiconductor processing methods of forming integrated circuitry Semiconductor processing methods of forming integrated circuitry are described. In one embodiment, memory circuitry and peripheral circuitry are formed over a substrate. The peripheral circuitry comprises first and second type MOS transistors. Second type halo impla... | 03/11/2008 |
| 7335933 | Dynamic random access memory cell and method for fabricating the same A DRAM cell and a method for fabricating the same are provided. The method includes: forming a trench in a substrate; forming a first capacitor dielectric layer on the surface of the trench; forming a conducting layer inside the trench; forming a second capacitor di... | 02/26/2008 |