Class 438/242 - Including transistor formed on trench sidewalls

Subclass of Class 438 - Semiconductor device manufacturing: process
Definition: Process wherein the additional diverse field effect transistor
No. of patents: 300
Last issue date: 10/11/2011

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Number	Title	Issue Date
8034682	Power device with trenches having wider upper portion than lower portion A method of forming a semiconductor device includes the following. Removing portions of a silicon layer such that a trench having sidewalls which fan out near the top of the trench to extend directly over a portion of the silicon layer is formed in the silicon layer...	10/11/2011
7846790	Method of fabricating semiconductor device having multiple gate dielectric layers and semiconductor device fabricated thereby A method of fabricating a semiconductor device having multiple gate dielectric layers and a semiconductor device fabricated thereby, in which the method includes forming an isolation layer defining first and second active regions in a semiconductor substrate. A pass...	12/07/2010
7833858	Superjunction trench device formation methods Methods for forming semiconductor structures are provided for a semiconductor device employing a superjunction structure and overlying trench with embedded control gate. An embodiment comprises forming interleaved first and second spaced-apart regions of first and s...	11/16/2010
7785959	Method of multi-port memory fabrication with parallel connected trench capacitors in a cell A method is provided for fabricating a multi-port memory in which a plurality of parallel connected capacitors are in a cell. A plurality of trench capacitors are formed which have capacitor dielectric layers extending along walls of the plurality of trenches, the p...	08/31/2010
7785960	Vertical channel transistor in semiconductor device and method of fabricating the same A method of fabricating a vertical channel transistor for a semiconductor device includes forming, on a substrate, a plurality of active pillars each having a gate electrode formed on and surrounding a lower portion thereof; forming a first insulation layer over the...	08/31/2010
7781285	Semiconductor device having vertical transistor and method of fabricating the same There are provided a semiconductor device having a vertical transistor and a method of fabricating the same. The method includes preparing a semiconductor substrate having a cell region and a peripheral circuit region. Island-shaped vertical gate structures two-dime...	08/24/2010
7767517	Semiconductor memory comprising dual charge storage nodes and methods for its fabrication A dual charge storage node memory device and methods for its fabrication are provided. In one embodiment a dielectric plug is formed comprising a first portion recessed into a semiconductor substrate and a second portion extending above the substrate. A layer of sem...	08/03/2010
7767518	Field effect transistor A field effect transistor is provided. The field effect transistor includes a channel region, electrically conductive channel connection regions, and a control region. The electrically conductive channel connection regions adjoin the channel region along with a tran...	08/03/2010
7741174	Methods of forming pad structures and related methods of manufacturing recessed channel transistors that include such pad structures Methods of forming pad structures are provided in which a first contact region and second contact regions are formed in an active region of a substrate. An insulating interlayer is formed on the substrate. The insulating interlayer has a first opening that exposes t...	06/22/2010
7704827	Semiconductor device and method for manufacturing the same An epitaxial layer is formed on an n+ semiconductor substrate by epitaxial growth. A gate trench is formed to the surface of gate trench so that the bottom of gate trench reaches middle of the epitaxial layer. A gate insulator is formed on the inner wall of gate tre...	04/27/2010
7615442	Method for fabricating trench metal-oxide-semiconductor field effect transistor A method for fabricating a trench metal-oxide-semiconductor field effect transistor is disclosed. The method comprises steps of providing a substrate with an epitaxy layer thereon and etching the epitaxy layer to form a trench structure; forming a gate oxide layer o...	11/10/2009
7504298	Method for forming memory cell and device A memory cell, device, and system include a memory cell having a shared digitline, a storage capacitor, and a plurality of access transistors configured to selectively electrically couple the storage capacitor with the shared digitline. The digitline couples with ad...	03/17/2009
7494865	Fabrication method of metal oxide semiconductor transistor A manufacturing method of metal oxide semiconductor transistor is provided. A substrate is provided. A source/drain extension region is formed in the substrate. A pad material layer with low dielectric constant is formed on the substrate. A trench is formed in the s...	02/24/2009
7485525	Method of manufacturing a multiple port memory having a plurality of parallel connected trench capacitors in a cell An integrated circuit is provided which includes a memory having multiple ports per memory cell for accessing a data bit within each of a plurality of the memory cells. Such memory includes an array of memory cells in which each memory cell includes a plurality of c...	02/03/2009
7445985	DRAM memory and method for fabricating a DRAM memory cell A DRAM memory cell arrangement having memory cells each having a trench capacitor and a fin field-effect transistor or FinFET for addressing the trench capacitor. The memory cells are arranged in cell rows which are offset with respect to one another and are separat...	11/04/2008
7445986	Memory cells with vertical transistor and capacitor and fabrication methods thereof Memory cells with vertical transistor and capacitor and fabrication methods thereof. The memory cell comprises a substrate with a trench. A capacitor is disposed at the bottom of the trench. A first conductive layer is electrically coupled to the capacitor. The firs...	11/04/2008
7425499	Methods for forming interconnects in vias and microelectronic workpieces including such interconnects Methods for forming interconnects in blind vias or other types of holes, and microelectronic workpieces having such interconnects. The blind vias can be formed by first removing the bulk of the material from portions of the back side of the workpiece without thinnin...	09/16/2008
7419871	Methods of forming semiconductor constructions The invention includes a method in which a semiconductor substrate is provided to have a memory array region, and a peripheral region outward of the memory array region. Paired transistors are formed within the memory array region, with such paired transistors shari...	09/02/2008
7387931	Semiconductor memory device with vertical channel transistor and method of fabricating the same In a semiconductor memory device having a vertical channel transistor a body of which is connected to a substrate and a method of fabricating the same, the semiconductor memory device includes a semiconductor substrate including a plurality of pillars arranged space...	06/17/2008
7371645	Method of manufacturing a field effect transistor device with recessed channel and corner gate device Fabrication of recessed channel array transistors (RCAT) with a corner gate device includes forming pockets between a semiconductor fin that includes a gate groove and neighboring shallow trench isolations that extend along longs sides of the semiconductor fin. A pr...	05/13/2008
7368777	Accumulation device with charge balance structure and method of forming the same An accumulation-mode field effect transistor includes a plurality of gates and a semiconductor region having a channel region adjacent to but insulated from each of the plurality of gates. The semiconductor region further includes a conduction region wherein the cha...	05/06/2008
7369436	Vertical NAND flash memory device Memory devices, arrays, and strings are included that facilitate the use of vertical floating gate memory cells in NAND architecture memory strings, arrays, and devices. NAND Flash memory strings, arrays, and devices, include vertical Flash memory cells to form NAND...	05/06/2008
7368344	Methods of reducing floating body effect Methods of reducing the floating body effect in vertical transistors are disclosed. The floating body effect occurs when an active region in a pillar is cut off from the substrate by a depletion region and the accompanying electrostatic potential created. In a prefe...	05/06/2008
7364971	Method for manufacturing semiconductor device having super junction construction A semiconductor device includes a body region, a drift region having a first part and a second part, and a trench gate electrode. The body region is disposed on the drift region. The first and second parts extend in an extending direction so that the second part is ...	04/29/2008
7361571	Method for fabricating a trench isolation with spacers A method for forming a shallow trench isolation (STI) in a semiconductor device, is presented. In one embodiment, the method includes successively forming a pad oxide and a pad nitride on a silicon substrate, successively etching the pad nitride, the pad oxide, and ...	04/22/2008
7354822	Method of forming a MOSFET with dual work function materials A vertical pass transistor used in a DRAM cell for maintaining a low total leakage current and providing adequate drive current is described together with a method of fabricating such a device. The transistor gate is engineered in lieu of the channel. The vertical p...	04/08/2008
7342274	Memory cells with vertical transistor and capacitor and fabrication methods thereof Memory cells with vertical transistor and capacitor and fabrication methods thereof. The memory cell comprises a substrate with a trench. A capacitor is disposed at the bottom of the trench. A first conductive layer is electrically coupled to the capacitor. The firs...	03/11/2008
7335558	Method of manufacturing NAND flash memory device A method of manufacturing a NAND flash memory device, including the steps of providing a semiconductor substrate in which a cell region and a select transistor region are defined; simultaneously forming a plurality of cell gates on the semiconductor substrate of the...	02/26/2008
7326611	DRAM arrays, vertical transistor structures and methods of forming transistor structures and DRAM arrays The invention includes a method of forming a semiconductor construction. Dopant is implanted into the upper surface of a monocrystalline silicon substrate. The substrate is etched to form a plurality of trenches and cross-trenches which define a plurality of pillars...	02/05/2008
7326995	Trench MIS device having implanted drain-drift region and thick bottom oxide A trench MIS device is formed in a P-epitaxial layer that overlies an N+ substrate. In one embodiment, the device includes a thick oxide layer at the bottom of the trench and an N-type drain-drift region that extends from the bottom of the trench to the substrate. T...	02/05/2008
7324367	Memory cell and method for forming the same A semiconductor memory cell structure having 4 F2 dimensions and method for forming the same. The memory cell is formed on a surface of a substrate and includes an active region formed in the substrate, a semiconductor post formed on the surface of the su...	01/29/2008
7323380	Single transistor vertical memory gain cell A high density vertical single transistor gain cell is realized for DRAM operation. The gain cell includes a vertical transistor having a source region, a drain region, and a floating body region therebetween. A gate opposes the floating body region and is separated...	01/29/2008
7320926	Shallow trench filled with two or more dielectrics for isolation and coupling for stress control A method for forming shallow trenches having different trench fill materials is described. A stop layer is provided on a substrate. A plurality of trenches is etched through the stop layer and into the substrate. A first layer is deposited over the stop layer and fi...	01/22/2008
7316956	Method for fabricating semiconductor device and wire with silicide A method for fabricating a wire with silicide is disclosed. First, a conductive layer is formed on a substrate. And, a hard mask layer is formed on the conductive layer. Then, the hard mask layer is used as a mask to remove a portion of the conductive layer. Afterwa...	01/08/2008
7316951	Fabrication method for a trench capacitor having an insulation collar The present invention provides a fabrication method for a trench capacitor having an insulation collar (10) in a silicon substrate (1), having the steps of: providing a trench (5) in the silicon substrate (1); providing the insulation col...	01/08/2008
7300852	Method for manufacturing capacitor of semiconductor element A method for manufacturing a capacitor of a semiconductor element including: forming a bottom electrode of the capacitor on a semiconductor substrate; performing rapid thermal nitrification (RTN) on the upper surface of the bottom electrode; performing a thermal pro...	11/27/2007
7291541	System and method for providing improved trench isolation of semiconductor devices A system and method is disclosed for providing improved trench isolation of semiconductor devices. An isolation trench of the present invention is manufactured as follows. A substrate of a semiconductor device is provided and a trench is etched in the substrate. The...	11/06/2007
7291884	Trench MIS device having implanted drain-drift region and thick bottom oxide A trench MIS device is formed in a P-epitaxial layer that overlies an N-epitaxial layer and an N+ substrate. In one embodiment, the device includes a thick oxide layer at the bottom of the trench and an N-type drain-drift region that extends from the bottom of the t...	11/06/2007
7282412	Trench semiconductor device having gate oxide layer with multiple thicknesses and processes of fabricating the same The a trench semiconductor device such as a power MOSFET the high electric field at the corner of the trench is diminished by increasing the thickness of the gate oxide layer at the bottom of the trench. Several processes for manufacturing such devices are described...	10/16/2007
7282401	Method and apparatus for a self-aligned recessed access device (RAD) transistor gate A method used in fabrication of a recessed access device transistor gate has increased tolerance for mask misalignment. One embodiment of the invention comprises forming a vertical spacing layer over a semiconductor wafer, then etching the vertical spacing layer and...	10/16/2007

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Class 438/242 - Including transistor formed on trench sidewalls