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| Number | Title | Issue Date |
| 8158476 | Integrated circuit fabrication A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two... | 04/17/2012 |
| 8076197 | Image sensor and method for fabricating the same A CMOS image sensor includes a substrate including silicon, a silicon germanium (SiGe) epitaxial layer formed over the substrate, the SiGe epitaxial layer formed through epitaxial growth and doped with a predetermined concentration level of impurities, an undoped si... | 12/13/2011 |
| 8043911 | Methods of forming semiconductor constructions The invention includes methods of forming semiconductor constructions in which a single etch is utilized to penetrate through a titanium-containing layer and partially into a silicon-containing layer beneath the titanium-containing layer. The etch can utilize CH | 10/25/2011 |
| 7981742 | Semiconductor device, data element thereof and method of fabricating the same A method of fabricating a semiconductor device is provided. The method comprises: (a) providing a first and a second conductor; (b) providing a conductive layer; (c) forming a part of the conductive layer into a data storage layer by a plasma oxidation process, wher... | 07/19/2011 |
| 7858470 | Memory device and fabrication thereof A semiconductor memory device. A trench capacitor disposed at a lower portion of a trench in a substrate, in which the trench capacitor comprises a filling electrode layer and a collar dielectric layer surrounding the filling electrode layer. The top of the collar d... | 12/28/2010 |
| 7776683 | Integrated circuit fabrication A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two... | 08/17/2010 |
| 7727836 | Semiconductor device and process for production thereof Disclosed herein is a semiconductor device with high reliability which has TFT of adequate structure arranged according to the circuit performance required. The semiconductor has the driving circuit and the pixel portion on the same substrate. It is characterized in... | 06/01/2010 |
| 7709319 | Semiconductor device and method of manufacturing the same Provided is a semiconductor device including a vertically oriented capacitor extending above the substrate surface and a method of manufacturing such devices in which cell, peripheral and boundary areas between the cell and peripheral areas are defined on a semicond... | 05/04/2010 |
| 7704826 | Leveling algorithm for semiconductor manufacturing equipment and related apparatus A method of reading surface levels of a field defined on a substrate using a sensing apparatus having at least one cell array composed of a plurality of cells, in which some of the cells constituting the at least one cell array are selected and designated as availab... | 04/27/2010 |
| 7678644 | Method and resulting structure for DRAM cell and peripheral transistor A method for fabricating DRAM cells, e.g., dynamic random access memory cells. The method includes providing a semiconductor substrate, e.g., silicon wafer. The method includes forming a plurality of NMOS transistor gate structures. Each of the NMOS gate structures ... | 03/16/2010 |
| 7674674 | Method of forming a dual gated FinFET gain cell A memory gain cell for a memory circuit, a memory circuit formed from multiple memory gain cells, and methods of fabricating such memory gain cells and memory circuits. The memory gain cell includes a storage device capable of holding a stored electrical charge, a w... | 03/09/2010 |
| 7635625 | Method for manufacturing image sensor Disclosed is a method for manufacturing an image sensor. The method includes forming a polysilicon layer on a semiconductor substrate having an active region, forming a sacrificial layer on the polysilicon layer, forming a photoresist pattern on the sacrificial laye... | 12/22/2009 |
| 7635624 | Dual gate structure for imagers and method of formation A device, as in an integrated circuit, includes diverse components such as transistors and capacitors. After conductive layers for all types of components are produced, a silicide layer is provided over conductive layers, reducing resistance. The device can be an im... | 12/22/2009 |
| 7622348 | Methods for fabricating an integrated circuit Methods are provided for reducing the aspect ratio of contacts to bit lines in fabricating an IC including logic and memory. The method includes the steps of forming a first group of device regions to be contacted by a first level of metal and a second group of memo... | 11/24/2009 |
| 7611944 | Integrated circuit fabrication A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two... | 11/03/2009 |
| 7601586 | Methods of forming buried bit line DRAM circuitry A method of forming buried bit line DRAM circuitry includes collectively forming a buried bit line forming trench, bit line vias extending from the bit line forming trench, and memory array storage node vias within a dielectric mass using only two masking steps. Con... | 10/13/2009 |
| 7566613 | Method of forming a dual gated FinFET gain cell A memory gain cell for a memory circuit, a memory circuit formed from multiple memory gain cells, and methods of fabricating such memory gain cells and memory circuits. The memory gain cell includes a storage device capable of holding a stored electrical charge, a w... | 07/28/2009 |
| 7563668 | Semiconductor device and method of manufacturing same A technique for enhancing the performance of a memory- and logic-equipped semiconductor device is provided. The semiconductor device comprises a semiconductor substrate (1), an insulating layer (19) on the semiconductor substrate (1), a pluralit... | 07/21/2009 |
| 7507622 | Semiconductor device and manufacturing method thereof A semiconductor device includes a semiconductor layer, an insulated-gate field effect transistor provided in the semiconductor layer, an etching stopper film provided above the insulated-gate field effect transistor, and an interlayer insulating layer provided above... | 03/24/2009 |
| 7498220 | Methods of fabricating semiconductor memory devices including different dielectric layers for the cell transistors and refresh transistors thereof Semiconductor memory devices include memory cell transistors having spaced apart memory cell transistor source and drain regions, and a memory cell transistor insulated gate electrode that includes a memory cell transistor gate dielectric layer. Refresh transistors ... | 03/03/2009 |
| 7494864 | Method for production of semiconductor device A method for production of a semiconductor device including the steps of: forming a gate insulating film, a polysilicon film and a first insulating film on a silicon substrate; patterning the first insulating film; forming a metal film; forming a silicide layer by r... | 02/24/2009 |
| 7482221 | Memory device and method of manufacturing a memory device The invention relates to a method of forming a memory device comprising a memory cell array and a peripheral portion. When forming the capacitors in the memory cell array, a sacrificial layer is deposited which is usually made of silicon dioxide and which is used fo... | 01/27/2009 |
| 7462534 | Methods of forming memory circuitry The invention includes methods of forming memory circuitry. In one implementation, a substrate is provided which has a memory array circuitry area and a peripheral circuitry area. The memory array circuitry area comprises transistor gate lines having a first minimum... | 12/09/2008 |
| 7442602 | Methods of fabricating phase change memory cells having a cell diode and a bottom electrode self-aligned with each other Integrated circuit devices are provided having a vertical diode therein. The devices include an integrated circuit substrate and an insulating layer on the integrated circuit substrate. A contact hole penetrates the insulating layer. A vertical diode is in a lower r... | 10/28/2008 |
| 7439125 | Contact structure for a stack DRAM storage capacitor A method for fabricating a contact structure for a stack storage capacitor includes forming the contact structure in a node contact region with contact openings, an insulating liner and a conductive filling material prior to the patterning of bit lines. ... | 10/21/2008 |
| 7439112 | Semiconductor device using partial SOI substrate and manufacturing method thereof A semiconductor device manufacturing method includes selectively removing portions of a buried oxide layer and first semiconductor layer in an SOI substrate having the first semiconductor layer formed above a semiconductor substrate with the buried oxide layer dispo... | 10/21/2008 |
| 7435642 | Method of evaluating the uniformity of the thickness of the polysilicon gate layer A method of evaluating the uniformity of the thickness of the polysilicon gate layer is provided. A substrate having a dense trenches area and a sparse trenches area is provided. A plurality of first trench isolation structures are formed in the sparse trenches area... | 10/14/2008 |
| 7390749 | Self-aligned pitch reduction A method for providing features in an etch layer with a memory region and a peripheral region is provided. A memory patterned mask is formed over a first sacrificial layer. A first set of sacrificial layer features is etched into the first sacrificial layer and a se... | 06/24/2008 |
| 7387929 | Capacitor in semiconductor device and method of manufacturing the same The present invention relates to a capacitor in semiconductor device and a method of manufacturing the same, wherein, owing to formation of a lower electrode and an upper electrode into a stack structure of a poly-silicon layer and an aluminum (Al) layer and formati... | 06/17/2008 |
| 7378311 | Method of forming memory cells in an array The invention includes a 6F2 DRAM array formed on a semiconductor substrate. The memory array includes a first memory cell. The first memory cell includes a first access transistor and a first data storage capacitor. A first load electrode of the first ac... | 05/27/2008 |
| 7374980 | Field effect transistor with thin gate electrode and method of fabricating same A field effect transistor and a method of fabricating the field effect transistor. The field effect transistor includes: a silicon body, a perimeter of the silicon body abutting a dielectric isolation; a source and a drain formed in the body and on opposite sides of... | 05/20/2008 |
| 7371645 | Method of manufacturing a field effect transistor device with recessed channel and corner gate device Fabrication of recessed channel array transistors (RCAT) with a corner gate device includes forming pockets between a semiconductor fin that includes a gate groove and neighboring shallow trench isolations that extend along longs sides of the semiconductor fin. A pr... | 05/13/2008 |
| 7367534 | Drop wire clamp A compression-type drop wire clamp that avoids damaging a signal carrying portion of a cable by applying a compressive force primarily to a support portion of a cable is disclosed herein. A plurality of holes may be included in a compression portion of the clamp to ... | 05/06/2008 |
| 7368776 | Semiconductor device comprising a highly-reliable, constant capacitance capacitor A semiconductor device, having a memory cell region and a peripheral circuit region, includes an insulating film, having an upper surface, formed on a major surface of a semiconductor substrate to extend from the memory cell region to the peripheral circuit region. ... | 05/06/2008 |
| 7364997 | Methods of forming integrated circuitry and methods of forming local interconnects In one implementation, field oxide is grown within bulk semiconductive material in a first circuitry area and not over immediately adjacent bulk semiconductive material in a second circuitry area. The field oxide is etched from the first circuitry area. After the et... | 04/29/2008 |
| 7361547 | Method for forming a capacitor for use in a semiconductor device A method for forming a capacitor for use in a semiconductor device having electrode plugs surrounded by an insulating film and connected to underlying contact pads, includes sequentially forming an etch stop film and a mold oxide film on the insulating film and the ... | 04/22/2008 |
| 7361588 | Etch process for CD reduction of arc material A method of reducing critical dimensions of a feature in a anti-reflective coating layer structure can utilize a polymerizing agent. The anti-reflective coating structure can be utilized to form various integrated circuit structures. The anti-reflective coating can ... | 04/22/2008 |
| 7361545 | Field effect transistor with buried gate pattern A field effect transistor includes a buried gate pattern that is electrically isolated by being surrounded by a tunneling insulating film. The field effect transistor also includes a channel region that is floated by source and drain regions, a gate insulating film,... | 04/22/2008 |
| 7361958 | Nonplanar transistors with metal gate electrodes A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first... | 04/22/2008 |
| 7358171 | Method to chemically remove metal impurities from polycide gate sidewalls An embodiment includes a process of forming a gate stack that acts to resist the redeposition to the semiconductive substrate of mobilized metal such as from a metal gate electrode. An embodiment also relates to a system that achieves the process. An embodiment also... | 04/15/2008 |
