"Radio has no future."
Lord Kelvin, British mathematician and physicist ; 1897
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8124474 | Method for producing electrode for electric double layer capacitor A method for producing an electrode for electric double layer capacitors is disclosed which includes: a step of mixing a particulate elastomer and a carbonaceous material with each other in a powdery form, thereby obtaining a powdery mixture; and a step of dry-formi... | 02/28/2012 |
| 8124475 | Integrated circuit arrangement with capacitor and fabrication method An integrated circuit arrangement contains an insulating region, which is part of a planar insulating layer, and a capacitor which contains: near and far electrode regions near and remote from the insulating region and a dielectric region. The capacitor and an activ... | 02/28/2012 |
| 8119476 | Methods of forming integrated circuit capacitors having sidewall supports and capacitors formed thereby In a method of forming a capacitor, a first mold layer pattern including a first insulating material may be formed on a substrate. The first mold layer pattern may have a trench. A supporting layer including a second insulating material may be formed in the trench. ... | 02/21/2012 |
| 8114732 | Method for manufacturing twin bit structure cell with AlO/nano-crystalline Si layer A method and system for forming a non-volatile memory structure. The method includes providing a semiconductor substrate and forming a gate dielectric layer overlying a surface region of the semiconductor substrate. A polysilicon gate structure is formed overlying t... | 02/14/2012 |
| 8088658 | Thin film capacitor and method of fabrication thereof Methods for fabricating a capacitor are provided. In the methods, a dielectric may be formed on a metal (e.g. nickel) substrate, and a copper electrode is formed thereon, followed by the thinning of the metal substrate from its non-coated face, and subsequently form... | 01/03/2012 |
| 8071438 | Semiconductor circuit A semiconductor memory device includes a substrate and an interconnect region carried by the substrate. A donor layer is coupled to the interconnect region through a bonding interface. An electronic device is formed with the donor layer, wherein the electronic devic... | 12/06/2011 |
| 8053308 | Method of forming a pattern and method of manufacturing a capacitor In a method of forming a pattern, a mold layer having an opening is formed on a substrate. A conductive layer is formed on the mold layer having the opening, the conductive layer having a substantially uniform thickness. A buffer layer pattern is formed in the openi... | 11/08/2011 |
| 8039343 | Scratch protection for direct contact sensors In capacitive sensor circuits where physical contact is required and excess pressure may be inadvertently applied to the sensor surface, aluminum is not sufficiently hard to provide “scratch” protection and may delaminate, causing circuit failure, even if passiv... | 10/18/2011 |
| 8030156 | Methods of forming DRAM arrays Methods of etching into silicon oxide-containing material with an etching ambient having at least 75 volume percent helium. The etching ambient may also include carbon monoxide, O2 and one or more fluorocarbons. The openings formed in the silicon oxide-co... | 10/04/2011 |
| 8026138 | Method for manufacturing semiconductor apparatus having saddle-fin transistor and semiconductor apparatus fabricated thereby A method for manufacturing a semiconductor memory apparatus may include forming a channel region and a gate region through a self-alignment etching process on a cell region; and forming a three-dimensional multi-channel region through an etching process using a firs... | 09/27/2011 |
| 8026137 | Production method of a capacitor A method for producing a capacitor having a good capacitance appearance factor and a low ESR comprising, as one electrode (anode), an electric conductor having pores and having formed on the surface thereof a dielectric layer and, as the other electrode (cathode), a... | 09/27/2011 |
| 8012823 | Methods of fabricating stack type capacitors of semiconductor devices Provided are methods of fabricating capacitors of semiconductor devices, the methods including: forming a lower electrode on a semiconductor substrate, performing a pre-process operation on the lower electrode for suppressing deterioration of the lower electrode dur... | 09/06/2011 |
| 8003461 | Method of fabricating efuse structure, resistor sturcture and transistor sturcture A method of fabricating an efuse structure, a resistor structure and a transistor structure. First, a work function metal layer, a polysilicon layer and a first hard mask layer are formed to cover a transistor region, a resistor region and an e-fuse region on a subs... | 08/23/2011 |
| 7989285 | Method of forming a film containing dysprosium oxide and hafnium oxide using atomic layer deposition The use of atomic layer deposition (ALD) to form a dielectric layer of hafnium oxide (HfO2) doped with dysprosium (Dy) and a method of fabricating such a combination gate and dielectric layer produces a reliable structure for use in a variety of electroni... | 08/02/2011 |
| 7989284 | DRAM cell transistor device and method A method for forming a memory device. The method provides a protective layer overlying a surface region of a substrate before threshold voltage implant. The method then includes depositing a photo resist layer and patterning the photo resist by selectively removing ... | 08/02/2011 |
| 7960226 | Method of forming on-chip decoupling capacitor with bottom electrode layer having surface roughness On-chip decoupling capacitor structures, and methods of fabricating such decoupling capacitors are disclosed. On-chip decoupling capacitors help to reduce or prevent L di/dt voltage droop on the power grid for high surge current conditions. The inclusion of one or m... | 06/14/2011 |
| 7927945 | Method for manufacturing semiconductor device having 4F2 transistor Provided is a method for manufacturing a semiconductor device having a 4F2 transistor. In the method, a gate stack is formed on a semiconductor substrate. A first interlayer dielectric including a contact hole which includes a first region and second regions Spacer ... | 04/19/2011 |
| 7927946 | Semiconductor device and manufacturing method of the same An interlayer insulating film (14) covering a ferroelectric capacitor is formed and a contact hole (19) reaching a top electrode (11a) is formed in the interlayer insulating film (14). An Al wiring (17) connected to the top ... | 04/19/2011 |
| 7923322 | Method of forming a capacitor A method of forming a capacitor includes forming a first capacitor electrode over a substrate. A substantially crystalline capacitor dielectric layer is formed over the first capacitor electrode. The substrate with the substantially crystalline capacitor dielectric ... | 04/12/2011 |
| 7923324 | Method for manufacturing capacitor of semiconductor device A method for manufacturing a capacitor of a semiconductor device includes forming a lower metal layer over a substrate, forming a dielectric layer over the lower metal layer, forming an upper metal layer over the dielectric layer, forming an upper electrode and a di... | 04/12/2011 |
| 7923323 | Metal capacitor including lower metal electrode having hemispherical metal grains Disclosed is a metal capacitor including a lower electrode having hemispherical metal grains thereon. The metal capacitor includes a lower metal electrode containing Ti, hemispherical metal grains containing Pd and formed on the lower metal electrode containing Ti, ... | 04/12/2011 |
| 7915116 | Relaxed-pitch method of aligning active area to digit line According to one aspect of the invention, a memory device is disclosed. The memory device comprises a substantially linear active area comprising a source and at least two drains defining a first axis. The memory device further comprises at least two substantially p... | 03/29/2011 |
| 7906392 | Pillar devices and methods of making thereof A method of making a semiconductor device includes providing an insulating layer containing a plurality of openings, forming a first semiconductor layer in the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion ... | 03/15/2011 |
| 7892916 | Semiconductor device and fabricating method thereof An upper electrode layer is processed into plural electrode shapes with lithography and subsequent dry etching to pattern plural upper electrodes, followed by conducting an RTA treatment at a treatment temperature of a value in a range from 400° C. to 1000° C. and... | 02/22/2011 |
| 7883960 | Method of manufacturing semiconductor device A method of manufacturing a semiconductor device includes forming a conductive layer over a semiconductor substrate, selectively removing the conductive layer for forming a resistance element and a gate electrode, forming sidewall spacers over sidewalls of the remai... | 02/08/2011 |
| 7829409 | Method of manufacturing silicon topological capacitors In accordance with the present invention, a novel method to fabricate topological capacitors is provided. The fabrication method of the instant invention is based upon a reversed surface topology utilizing deep reactive ion etching to establish conductive capacitive... | 11/09/2010 |
| 7820505 | Integrated circuit arrangement with capacitor and fabrication method An integrated circuit arrangement contains an insulating region, which is part of a planar insulating layer, and a capacitor which contains: near and far electrode regions near and remote from the insulating region and a dielectric region. The capacitor and an activ... | 10/26/2010 |
| 7816202 | Method for fabricating capacitor in semiconductor device A method for fabricating a capacitor includes providing a substrate having a capacitor region is employed, forming a first Ru1−xOx layer over the substrate, forming a Ru layer for a lower electrode over the first Ru1−xOx | 10/19/2010 |
| 7781283 | Split-gate DRAM with MuGFET, design structure, and method of manufacture A method of manufacturing a dynamic random access memory cell includes: forming a substrate having an insulating region over a conductive region; forming a fin of a fin-type field effect transistor (FinFET) device over the insulating region; forming a storage capaci... | 08/24/2010 |
| 7781284 | Semiconductor device and method of manufacturing the same There is provided a semiconductor device which comprises a first interlayer insulating film (first insulating film) formed over a silicon (semiconductor) substrate, a capacitor formed on the first interlayer insulating film and having a lower electrode, a dielectric... | 08/24/2010 |
| 7776682 | Ordered porosity to direct memory element formation Disclosed are methods and systems for improving cell-to-cell repeatability of electrical performance in memory cells. The methods involve forming an electrically non-conducting material having ordered porosity over a passive layer. The ordered porosity can facilitat... | 08/17/2010 |
| 7759187 | Metal plating using seed film A seed film and methods incorporating the seed film in semiconductor applications is provided. The seed film includes one or more noble metal layers, where each layer of the one or more noble metal layers is no greater than a monolayer. The seed film also includes e... | 07/20/2010 |
| 7749834 | Method of fabricating semiconductor devices having buried contact plugs A method includes forming a lower dielectric layer on a semiconductor substrate, forming a bit line landing pad and a storage landing pad that penetrate the lower dielectric layer, covering the lower dielectric layer, the bit line landing pad, and the storage landin... | 07/06/2010 |
| 7745279 | Capacitor that includes high permittivity capacitor dielectric A decoupling capacitor is formed on a semiconductor substrate that includes a silicon surface layer. A substantially flat bottom electrode is formed in a portion of the semiconductor surface layer. A capacitor dielectric overlies the bottom electrode. The capacitor ... | 06/29/2010 |
| 7745280 | Metal-insulator-metal capacitor structure A metal-insulator-metal capacitor structure includes a lower electrode, a buffer layer, a barrier layer, a dielectric layer and an upper electrode. The lower electrode is disposed in the buffer layer. The barrier layer covers part of the lower electrode and is dispo... | 06/29/2010 |
| 7736969 | DRAM layout with vertical FETS and method of formation DRAM cell arrays having a cell area of about 4F2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material and are provided below a surface of the substrate. The ... | 06/15/2010 |
| 7732273 | Semiconductor device manufacturing method and semiconductor device A manufacturing method of a semiconductor device having a highly reliable capacitor, and the semiconductor device are provided. The semiconductor device manufacturing method according to the present invention includes: a first step of forming a first electrode of a ... | 06/08/2010 |
| 7700432 | Method of fabricating a vertical transistor and capacitor A process and an architecture related to a vertical MOSFET device and a capacitor for use in integrated circuits. The integrated circuit structure includes a semiconductor layer with a major surface and further including a first doped region formed in the surface. A... | 04/20/2010 |
| 7700431 | Method for manufacturing a semiconductor device having polysilicon plugs A method for manufacturing a DRAM device on a silicon substrate includes: forming cell transistors in a memory cell area and other transistors in a peripheral circuit area; forming polysilicon plugs connected to diffused regions of the cell transistors and metallic ... | 04/20/2010 |
| 7696040 | Method for fabrication of fin memory structure A semiconductor fin memory structure and a method for fabricating the semiconductor fin memory structure include a semiconductor fin-channel within a finFET structure that is contiguous with and thinner than a conductor fin-capacitor node within a fin-capacitor stru... | 04/13/2010 |