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| Number | Title | Issue Date |
| 8440522 | Increasing an electrical resistance of a resistor by oxidation A method for increasing an electrical resistance of a resistor that is within a semiconductor structure. A fraction of a surface layer of the resistor is oxidized with oxygen particles. In an embodiment, the fraction of the surface layer is heated by a beam of parti... | 05/14/2013 |
| 8426267 | Semiconductor device and method of manufacturing the same The semiconductor device includes a first MIS transistor including a gate insulating film 92, a gate electrode 108 formed on the gate insulating film 92 and source/drain regions 154, a second MIS transistor including a gate insulating fil... | 04/23/2013 |
| 8420478 | Controlled localized defect paths for resistive memories Controlled localized defect paths for resistive memories are described, including a method for forming controlled localized defect paths including forming a first electrode forming a metal oxide layer on the first electrode, masking the metal oxide to create exposed... | 04/16/2013 |
| 8389355 | Semiconductor integrated circuit device having MIM capacitor and method of fabricating the same In a semiconductor integrated circuit device and a method of formation thereof, a semiconductor device comprises: a semiconductor substrate; an insulator at a top portion of the substrate, defining an insulator region; a conductive layer pattern on the substrate, th... | 03/05/2013 |
| 8349682 | Method for fabricating metal gate transistor and polysilicon resistor An integrated method includes fabricating a metal gate transistor and a polysilicon resistor structure. A photoresistor layer is defined by an SAB photo mask and covers a part of a high resistance structure of the polysilicon resistor. When the dummy gate of the tra... | 01/08/2013 |
| 8338249 | Semiconductor device and method for manufacturing the same having improved polarization reversal characteristic A method for manufacturing a semiconductor device comprises: forming a lower electrode on a semiconductor substrate, sputtering a ferroelectric film on the lower electrode using a target, thermal treating the ferroelectric film in an atmosphere containing oxygen in ... | 12/25/2012 |
| 8324046 | Poly resistor and poly eFuse design for replacement gate technology Methods for fabricating a semiconductor device are disclosed. In an example, a method includes forming an isolation region on a substrate, wherein the isolation region extends a depth into the substrate from a substrate surface; forming a recess in the isolation reg... | 12/04/2012 |
| 8324045 | Method of forming semiconductor device having common node that contacts plural stacked active elements and that has resistive memory elements corresponding to the active elements A semiconductor device and a method of forming the same are provided. The method includes preparing a semiconductor substrate. Insulating layers may be sequentially formed on the semiconductor substrate. Active elements may be formed between the insulating layers. A... | 12/04/2012 |
| 8263454 | Embedded semiconductor device including planarization resistance patterns and method of manufacturing the same An embedded semiconductor device which a logic region and the memory region are planarized with planarization resistance patterns and a method of manufacturing the same are disclosed. The embedded semiconductor device includes a substrate, gates formed on the substr... | 09/11/2012 |
| 8263455 | Method of forming variable resistance memory device Provided are a method of forming an electrode of a variable resistance memory device and a variable resistance semiconductor memory device using the method. The method includes: forming a heat electrode; forming a variable resistance material layer on the heat elect... | 09/11/2012 |
| 8232161 | Semiconductor device and manufacturing method of the same A trench is formed so as to reach a p−-type epitaxial layer from an upper surface of a source region. A gate electrode is formed so as to bury the trench. Each of body contact trenches is formed away from the gate electrode. A body contact region is for... | 07/31/2012 |
| 8183107 | Semiconductor devices with improved local matching and end resistance of RX based resistors Semiconductor devices are formed with reduced variability between close proximity resistors, improved end resistances, and reduced random dopant mismatch. Embodiments include ion implanting a dopant, such as B, at a relatively high dosage, e.g. about 4 to about 6 ke... | 05/22/2012 |
| 8168493 | Semiconductor memory device and method of manufacturing the same Provided are a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a semiconductor substrate including a first active region and a second active region, a gate electrode including a sili... | 05/01/2012 |
| 8143121 | DRAM cell with double-gate fin-FET, DRAM cell array and fabrication method thereof A transistor structure includes a semiconductor substrate having a top surface and sidewalls extending downward from the top surface, wherein each of the sidewall comprises a vertical upper sidewall surface and a lower sidewall recess laterally etched into the semic... | 03/27/2012 |
| 8133780 | Semiconductor integrated circuit device and process for manufacturing the same A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer consti... | 03/13/2012 |
| 8133779 | Method of fabricating a semiconductor device A conductive film is formed to extend from a bottom and a sidewall of a recess formed in an interlayer insulating film onto a top surface of the interlayer insulating film. Dry etching of the conductive film is performed such that a portion of the conductive film re... | 03/13/2012 |
| 8114731 | Integrated high voltage capacitor having capacitance uniformity structures and a method of manufacture therefor The present invention provides an integrated high voltage capacitor, a method of manufacture therefore, and an integrated circuit chip including the same. The integrated high voltage capacitor, among other features, includes a first capacitor plate (120) loca... | 02/14/2012 |
| 8101481 | Spacer lithography processes A spacer lithography process for creating negative features such as, for example, cut-lines, or trenches, and holes is provided. The negative spacer lithography process may be utilized along with positive spacer lithography to fabricate electronic devices or the lik... | 01/24/2012 |
| 8084321 | DRAM cell with enhanced capacitor area and the method of manufacturing the same A dynamic random access memory (DRAM) cell and the method of manufacturing the same are provided. The DRAM cell includes a cell transistor and a cell capacitor. The cell capacitor includes a first, second and third dielectric layer, and a first, second and third cap... | 12/27/2011 |
| 8071437 | Method of fabricating efuse, resistor and transistor A method of fabricating an efuse, a resistor and a transistor includes the following steps: A substrate is provided. Then, a gate, a resistor and an efuse are formed on the substrate, wherein the gate, the resistor and the efuse together include a first dielectric l... | 12/06/2011 |
| 8062942 | Method for fabricating multi-resistive state memory devices A treated conductive element is provided. A conductive element can be treated by depositing either a reactive metal or a very thin layer of material on the conductive element. The reactive metal (or very thin layer of material) would typically be sandwiched between ... | 11/22/2011 |
| 8058125 | Poly resistor on a semiconductor device The present disclosure provides a poly resistor on a semiconductor device and a method of fabricating the same. In an embodiment, a poly silicon resistor device is formed by providing a substrate having a first region and a second region. A dummy gate stack is forme... | 11/15/2011 |
| 8053307 | Method of fabricating semiconductor device with cell epitaxial layers partially overlap buried cell gate electrode A semiconductor device may include a substrate having a cell active region. A cell gate electrode may be formed in the cell active region. A cell gate capping layer may be formed on the cell gate electrode. At least two cell epitaxial layers may be formed on the cel... | 11/08/2011 |
| 8034681 | Method of forming flash memory device having inter-gate plug A method of forming a non-volatile memory device includes the following steps. First and second cell gates are formed in a cell region. First and second peripheral gates are formed in a peripheral-region. A first insulating layer is formed over the first and second ... | 10/11/2011 |
| 7985644 | Methods for forming fully segmented salicide ballasting (FSSB) in the source and/or drain region Transistor structures for relatively even current balancing within a device and methods for fabricating the same are disclosed. These devices can be used in relatively compact MOSFET Electrostatic Discharge (ESD) protection structures, such as in snapback devices. O... | 07/26/2011 |
| 7977183 | Semiconductor device and method of manufacturing same To provide a technique capable of improving the reliability of a semiconductor device even if the downsizing thereof is advanced. The technical idea of the present invention lies in the configuration in which in a first to a third silicon nitride film to be f... | 07/12/2011 |
| 7951664 | Methods of manufacturing resistors and structures thereof Methods of manufacturing resistors, methods of manufacturing semiconductor devices, and structures thereof are disclosed. In one embodiment, a method of fabricating a resistor includes forming a transistor material stack over a workpiece and patterning the transisto... | 05/31/2011 |
| 7951663 | Semiconductor device and method of forming IPD structure using smooth conductive layer and bottom-side conductive layer A semiconductor device is made by forming a smooth conductive layer over a substrate. A first insulating layer is formed over a first surface of the smooth conductive layer. A first conductive layer is formed over the first insulating layer. A second insulating laye... | 05/31/2011 |
| 7932146 | Metal gate transistor and polysilicon resistor and method for fabricating the same A method for fabricating metal gate transistors and a polysilicon resistor is disclosed. First, a substrate having a transistor region and a resistor region is provided. A polysilicon layer is then formed on the substrate to cover the transistor region and the resis... | 04/26/2011 |
| 7927944 | ESD protection transistor An electrostatic discharge (ESD) transistor structure includes a self-aligned outrigger less than 0.4 microns from a gate electrode that is 50 microns wide. The outrigger is fabricated on ordinary logic transistors of an integrated circuit without severely affecting... | 04/19/2011 |
| 7919368 | Area-efficient electrically erasable programmable memory cell Electrically erasable programmable “read-only” memory (EEPROM) cells in an integrated circuit, and formed by a single polysilicon level. The EEPROM cell consists of a coupling capacitor and a combined read transistor and tunneling capacitor. The capacitance of t... | 04/05/2011 |
| 7910427 | Semiconductor integrated circuit device and process for manufacturing the same A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer consti... | 03/22/2011 |
| 7906391 | Reducing leakage currents in memories with phase-change material A memory cell including a phase-change material may have reduced leakage current. The cell may receive signals through a buried wordline in one embodiment. The buried wordline may include a sandwich of a more lightly doped N type region over a more heavily doped N t... | 03/15/2011 |
| 7888201 | Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors A static memory element includes a first inverter having an input coupled to a left bit node and an output coupled to a right bit node. A second inverter has an input coupled to the right bit node and an output coupled to the left right bit node. A first fully deple... | 02/15/2011 |
| 7883959 | Semiconductor processing methods The invention includes methods of forming electrically conductive material between line constructions associated with a peripheral region or a pitch region of a semiconductor substrate. The electrically conductive material can be incorporated into an electrically-gr... | 02/08/2011 |
| 7879671 | Method for manufacturing a semiconductor device that is less prone to DC failures brought about by unwanted defects on capacitors therein A method for manufacturing a semiconductor device that is less prone to DC failures brought about by unwanted defects on capacitors in the device is presented. Manufacturing defects such as scratches are known to occur when making capacitors and that these defects a... | 02/01/2011 |
| 7875515 | Method for manufacturing capacitor of semiconductor device A method for manufacturing a capacitor of a semiconductor device includes: forming an interlayer insulating film including a contact plug over a semiconductor substrate; forming a first stack film including a capacitor oxide film and a nitride film over the interlay... | 01/25/2011 |
| 7863128 | Non-volatile memory device with improved erase speed A memory device may include a substrate, a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may also include a second dielectric layer formed over the charge storage element and a... | 01/04/2011 |
| 7855113 | Method for fabricating semiconductor memory device A method for fabricating a semiconductor memory device includes: forming a lower conductive layer over a semiconductor substrate; forming an insulation layer over the lower conductive layer; etching the insulation layer to form a contact hole that exposes a portion ... | 12/21/2010 |
| 7838360 | Memory array with surrounding gate access transistors and capacitors with global and staggered local bit lines A memory array with staggered local data/bit lines extending generally in a first direction formed in an upper surface of a substrate and memory cell access transistors extending generally upward and aligned generally atop a corresponding local data/bit line. Select... | 11/23/2010 |
