Did You Know...
...Chester Carlson was a patent agent who tired of having to make multiple copies of patent applications using the only duplication method available at the time: carbon paper. In 1959 he came up with a new copying system and took it to IBM for evaluation. The "experts" at IBM determined potential sales to be only 5,000 units because people wouldn't want to use a bulky machine when they had carbon paper. Carlson's invention was the xerography process, the company founded on the system is Xerox.
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| Number | Title | Issue Date |
| 7351620 | Methods of forming semiconductor constructions The invention includes BIFETRAM devices. Such devices comprise a bipolar transistor in combination with a field effect transistor (FET) in a three-dimensional stacked configuration. The memory devices can be incorporated within semiconductor-on-insulator (SOI) const... | 04/01/2008 |
| 7285830 | Lateral bipolar junction transistor in CMOS flow An improved lateral bipolar junction transistor and a method of forming such a lateral bipolar transistor without added mask in CMOS flow on a p-substrate are disclosed. The CMOS flow includes patterning and n-well implants; pattern and implant pocket implants for c... | 10/23/2007 |
| 7276744 | Semiconductor device and method of manufacturing the same This invention is intended to provide an HBT capable of achieving, if the HBT is a collector-up HBT, the constriction of the emitter layer disposed directly under an external base layer, and reduction in base-emitter junction capacity, or if the HBT is an emitter-up... | 10/02/2007 |
| 7169654 | Method of forming a semiconductor device A method of integrating a non-MOS transistor device and a CMOS electronic device on a semiconductor substrate includes forming openings within an active semiconductor layer in first and second regions of a semiconductor substrate. The first region corresponds to a n... | 01/30/2007 |
| 7166504 | Semiconductor device manufacturing method A semiconductor device manufacturing method is provided which is capable of suppressing variation of the resistance value of resistive interconnection and preventing variation of transistor performance. A gate electrode and a resistive interconnection are formed on ... | 01/23/2007 |
| 7144767 | NFETs using gate induced stress modulation A method for manufacturing an integrated circuit comprising a plurality of semiconductor devices including an n-type field effect transistor and a p-type field effect transistor by covering the p-type field effect transistor with a mask, and oxidizing a portion of a... | 12/05/2006 |
| 7049205 | Stacked capacitor and method for preparing the same The present invention discloses a stacked capacitor having interdigital electrodes and method for preparing the same. The stacked capacitor comprises a first interdigital electrode, a second interdigital electrode and a dielectric material sandwiched between the fir... | 05/23/2006 |
| 7045408 | Integrated circuit with improved channel stress properties and a method for making it An integrated circuit is described that comprises a PMOS transistor and an NMOS transistor that are formed on a semiconductor substrate. A silicate glass layer is formed on only the PMOS transistor or the NMOS transistor; and an etch stop layer is formed on the sili... | 05/16/2006 |
| 6858443 | Methods of forming ferroelectric capacitors on protruding portions of conductive plugs having a smaller cross-sectional size than base portions thereof Ferroelectric capacitors, etc. are disclosed that include a conductive plug that has a base portion of a first cross-sectional width and a protruding portion that protrudes from the base portion and has a second cross-sectional width that is less than the first cros... | 02/22/2005 |
| 6821837 | Stack-film trench capacitor and method for manufacturing the same A trench capacitor includes an electrode having a first conductive area formed in a trench provided in a substrate, and a second conductive area extending from a bottom of the trench, the second conductive area being electrically coupled to the first conductive area... | 11/23/2004 |
| 6784065 | Bipolar transistor with ultra small self-aligned polysilicon emitter and method of forming the transistor A low-power bipolar transistor is formed to have an intrinsic emitter region with a sub-lithographic width, and an oxide layer that is self aligned to an overlying extrinsic emitter. The small extrinsic emitter region reduces the maximum current that can flow throug... | 08/31/2004 |
| 6780702 | Method of reducing device parasitic capacitance using underneath crystallographically selective wet etching When InP DHBTs are located in parallel to a crystallographical direction of , there are several advantages in the aspect of device property such as reliability. But, in case of a direction parallel to a general , there exists the limitation i... | 08/24/2004 |
| 6767810 | Method to increase substrate potential in MOS transistors used in ESD protection circuits An integrated circuit located between isolation trenches at the surface of a semiconductor chip comprising a first well of a first conductivity type having a first resistivity. This first well has a shallow buried region of higher resistivity than the first resistiv... | 07/27/2004 |
| 6767783 | Self-aligned transistor and diode topologies in silicon carbide through the use of selective epitaxy or selective implantation A method of making vertical diodes and transistors in SiC is provided. The method according to the invention uses a mask (e.g., a mask that has been previously used for etching features into the device) for selective epitaxial growth or selective ion implantation. I... | 07/27/2004 |
| 6764921 | Semiconductor device and method for fabricating the same A semiconductor device of the present invention includes a MISFET provided in an element formation region Re of a semiconductor substrate 11 and a trench isolation 13 surrounding the sides of the element formation region Re. An oxygen-passage-suppressi... | 07/20/2004 |
| 6686233 | Integration of high voltage self-aligned MOS components The invention relates to a method for forming a high voltage NMOS transistor together with a low voltage NMOS transistor and a low voltage PMOS transistor, respectively, in an n-well CMOS process by adding solely two additional process steps to a conventi... | 02/03/2004 |
| 6667202 | Semiconductor device and method for making the same A semiconductor device which has: a bipolar transistor having a collector region of a second conductivity type formed from the surface of a semiconductor substrate of a first conductivity type, a base region of a first conductivity type formed from the su... | 12/23/2003 |
| 6638807 | Technique for gated lateral bipolar transistors An improved structure and method for gated lateral bipolar transistors are provided. Embodiments of the present invention capitalize on opposing sidewalls and adjacent conductive sidewall members to conserve available surface space on the semiconductor ch... | 10/28/2003 |
| 6569730 | High voltage transistor using P+ buried layer A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This... | 05/27/2003 |
| 6551869 | Lateral PNP and method of manufacture A lateral PNP is disclosed in which a substrate of a first conductivity type is used. On top of the substrate a buried region of a second conductivity type is formed. A lightly doped collector region is located above the buried region. The lateral PNP als... | 04/22/2003 |
| 6537887 | Integrated circuit fabrication An integrated circuit and a process for making the same are provided. The circuit has a nitrogen implanted emitter window, wherein the nitrogen has been implanted into the emitter window after the emitter window etch, but prior to the emitter conductor de... | 03/25/2003 |
| 6448125 | Electronic power device integrated on a semiconductor material and related manufacturing process An electronic power device is integrated on a substrate of semiconductor material having a first conductivity type, on which an epitaxial layer of the same type of conductivity is grown. The power device comprises a power stage PT and a control stage CT, ... | 09/10/2002 |
| 6436747 | Method of fabricating semiconductor device After phosphorus is ion implanted into a portion of a polysilicon film, first RTA is performed. After boron is ion implanted into another portion of the polysilicon film, the polysilicon film is patterned to form a gate electrode and a resistor film. A TE... | 08/20/2002 |
| 6384433 | Voltage variable resistor from HBT epitaxial layers A voltage variable resistor formed on heterojunction bipolar transistor epitaxial material includes a current channel made on emitter material. Emitter mesas separated by a recess provide the contacts for the voltage variable resistor. Each mesa is topped... | 05/07/2002 |
| 6365448 | Structure and method for gated lateral bipolar transistors An improved structure and method for gated lateral bipolar transistors is provided. The present invention capitalizes on opposing sidewall structures and adjacent conductive sidewall members to conserve available surface space on the semiconductor chips. ... | 04/02/2002 |
| 6352887 | Merged bipolar and CMOS circuit and method A method for fabricating a BiCMOS integrated circuit. The method includes the steps of forming in a single implantation step a base region 211 of a bipolar transistor and a p-well 212 of an n-channel MOS transistor; and forming in a single implantation st... | 03/05/2002 |
| 6316317 | Nonvolatile semiconductor memory device including two-transistor type memory cells and its manufacturing method In a nonvolatile semiconductor memory device including a plurality of memory cells each formed by one selection transistor and one memory transistor connected in series, the thickness of a first gate insulating layer of the selection transistor is smaller... | 11/13/2001 |
| 6271069 | Method of making an article comprising an oxide layer on a GaAs-based semiconductor body Disclosed are a method of making GaAs-based enhancement-type MOS-FETs, and articles (e.g., GaAs-based ICs) that comprise such a MOS-FET. The MOS-FETs are planar devices, without etched recess or epitaxial re-growth, with gate oxide that is primarily Ga | 08/07/2001 |
| 6265277 | Method for making a bipolar transistor for the protection of an integrated circuit against electrostatic discharges In a method for the making of a lateral bipolar transistor, the formation of a field oxide layer on the surface of the substrate, between the collector and the emitter of the protection transistor, is avoided. The lateral bipolar transistors made by the d... | 07/24/2001 |
| 6245609 | High voltage transistor using P+ buried layer A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This... | 06/12/2001 |
| 6235558 | Method for fabricating semiconductor device There is provided a method for stably fabricating a TFT having a GOLD structure capable of ensuring sufficiently high ON-state current and sufficiently low OFF-state current at the same time and superior in hot carrier resistance. The method includes form... | 05/22/2001 |
| 6213869 | MOSFET-type device with higher driver current and lower steady state power dissipation A coupling capacitor is coupled between the gate and the body region of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The body region of the MOSFET is electrically isolated to form a floating body region. The capacitance of the coupling ca... | 04/10/2001 |
| 6165848 | Method for the production of a MOS-controlled power semiconductor component The invention relates to a method for the production of a MOS-controlled power semiconductor component (30), which power semiconductor component (30) comprises, in a common substrate (31), a plurality of component cells which are arranged next to one anot... | 12/26/2000 |
| 6159784 | Method of producing semiconductor device A method of producing a semiconductor device by which the resistivities of the base, collector, and source/drain regions in a Bi-CMOS are decreased and the production step is simplified. A method of producing a semiconductor device comprising the steps of... | 12/12/2000 |
| 6110523 | Method of manufacturing a semiconductor memory device A semiconductor memory device and method of fabricating same is provided that has a plurality of ferroelectric memory cells and reference cells. The semiconductor memory device includes a capacitor of each memory cell being the same size as that of each r... | 08/29/2000 |
| 6093613 | Method for making high gain lateral PNP and NPN bipolar transistor compatible with CMOS for making BICMOS circuits A method and lateral bipolar transistor structure are achieved, with high current gain, compatible with CMOS processing to form BiCMOS circuits. Making a lateral PNP bipolar involves forming an N- well in a P- doped silicon substrate... | 07/25/2000 |
| 6071768 | Method of making an efficient NPN turn-on in a high voltage DENMOS transistor for ESD protection A high voltage DENMOS transistor (10) having improved ESD protection. The transistor (10) is optimized to provide maximum substrate current in order to turn on the inherent lateral npn transistor during an ESD event so that the lateral npn can dissipate t... | 06/06/2000 |
| 6051456 | Semiconductor component and method of manufacture A semiconductor component includes an asymmetric transistor having two lightly doped drain regions (1300, 1701), a channel region (1702), a source region (1916) located within the channel region (1702), a drain region located outside the channel region (1... | 04/18/2000 |
| 6033964 | System for enhancing the performance of a circuit by reducing the channel length of one or more transistors Generally, decreasing the length of the channel in a CMOS transistor increases the speed of the transistor. However, the degree that the channel can be minimized is limited due to Hot Carrier Injection ("HCI"), which is related to the drain to source volt... | 03/07/2000 |
| 6030453 | III-V epitaxial wafer production A production process for protecting the surface of compound semiconductor wafers includes providing a multi-wafer epitaxial production system with a transfer and load module, a III-V growth chamber and an insulator chamber. The wafer is placed in the tran... | 02/29/2000 |
