Celebrity Inventors
Comic actor Danny Kaye received patent D166,807 for the co-design of "Blowout Toy or the Like". It's similar to one of those toys that unravels when you blow into at a birthday party except Kaye's has three blowouts going in different directions, not just one.
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| Number | Title | Issue Date |
| 8110463 | Method of fabricating semiconductor device A method of fabricating a semiconductor device includes a first step of forming a defect suppression film suppressing increase in a defect due to implantation of an impurity on a semiconductor substrate, a second step of forming an active region on a surface of the ... | 02/07/2012 |
| 8048734 | Bipolar transistor and method for making same One or more embodiments of the invention relate to a method of making a heterojunction bipolar transistor, including: forming a collector layer; forming a stack of at least a second dielectric layer overlying a first dielectric layer, the stack formed over the colle... | 11/01/2011 |
| 7932145 | Method of forming a bipolar transistor and semiconductor component thereof A semiconductor component is formed using the following processes: (a) forming a first dielectric layer over the semiconductor substrate; (b) forming a base electrode for the bipolar transistor over the dielectric layer; (c) forming an oxide nitride structure over t... | 04/26/2011 |
| 7897452 | Method of producing a semiconductor device with an aluminum or aluminum alloy rear electrode A method of producing a semiconductor device having a thickness of 90 μm to 200 μm and with an electrode on the rear surface, which achieves a high proportion of non-defective devices by optimizing the silicon concentration and thickness of the aluminum-silicon el... | 03/01/2011 |
| 7871881 | Method for fabrication of a capacitor, and a monolithically integrated circuit comprising such a capacitor A method for fabrication of a monolithically integrated SOI substrate capacitor has the steps of: forming an insulating trench, which reaches down to the insulator and surrounds a region of the monocrystalline silicon of a SOI structure, doping the monocrystalline s... | 01/18/2011 |
| 7811879 | Process for PCM integration with poly-emitter BJT as access device Techniques for forming a memory cell. An aspect of the invention includes forming FET gate stacks and sacrificial cell gate stacks over the substrate. Spacer layers are then formed around the FET gate stacks and around the sacrificial cell gate stacks. The sacrifici... | 10/12/2010 |
| 7642154 | BiCMOS device and method of manufacturing a biCMOS device A biCMOS device including a bipolar transistor and a Polysilicon/Insulator/Polysilicon (PIP) capacitor is disclosed. A biCMOS device may have a relatively low series resistance at a bipolar transistor. A bipolar transistor may have a desirable amplification rate. | 01/05/2010 |
| 7638386 | Integrated CMOS and bipolar devices method and structure A method is provided for forming bipolar (103) and MOS (105) semiconductor devices in a common substrate (46), comprising, forming a combination comprising an MOS device (105) in a first region (44) of the substrate (46) and... | 12/29/2009 |
| 7435643 | Fabrication method of a dynamic random access memory A dynamic random access memory (DRAM) cell is described, including a semiconductor pillar on a substrate, a capacitor on a lower portion of a sidewall of the pillar, and a vertical transistor on an upper portion of the sidewall of the pillar. The capacitor includes ... | 10/14/2008 |
| 7371650 | Method for producing a transistor structure A method for fabricating a transistor structure with a first and a second bipolar transistor having different collector widths is presented. The method includes providing a semiconductor substrate, introducing a first buried layer of the first bipolar transistor and... | 05/13/2008 |
| 7361562 | Method of manufacturing semiconductor device Provided is a method of manufacturing a semiconductor device capable of forming a thin high-quality gate oxide layer by suppressing occurrence of recoiled oxygen due to ion implanting. The method of manufacturing a semiconductor device includes steps of: removing an... | 04/22/2008 |
| 7351620 | Methods of forming semiconductor constructions The invention includes BIFETRAM devices. Such devices comprise a bipolar transistor in combination with a field effect transistor (FET) in a three-dimensional stacked configuration. The memory devices can be incorporated within semiconductor-on-insulator (SOI) const... | 04/01/2008 |
| 7339235 | Semiconductor device having SOI structure and manufacturing method thereof A fine semiconductor device having a short channel length while suppressing a short channel effect. Linearly patterned or dot-patterned impurity regions 104 are formed in a channel forming region 103 so as to be generally parallel with the channel dire... | 03/04/2008 |
| 7335547 | Method for effective BiCMOS process integration According to an exemplary embodiment, a method for integrating bipolar and CMOS devices on a substrate, where the substrate includes bipolar and CMOS regions and has a sacrificial oxide layer situated thereon, includes removing a portion of the sacrificial oxide lay... | 02/26/2008 |
| 7332410 | Method of epitaxial-like wafer bonding at low temperature and bonded structure A process for bonding oxide-free silicon substrate pairs and other substrates at low temperature. This process involves modifying the surface of the silicon wafers to create defect regions, for example by plasma-treating the surface to be bonded with a or boron-cont... | 02/19/2008 |
| 7329570 | Method for manufacturing a semiconductor device An exemplary method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a P-well and an N-well for high voltage (HV) devices and a first well in a low voltage/medium voltage (LV/MV) region for a logic device, ... | 02/12/2008 |
| 7323386 | Method of fabricating semiconductor device containing dielectrically isolated PN junction for enhanced breakdown characteristics A semiconductor device includes a field shield region that is doped opposite to the conductivity of the substrate and is bounded laterally by dielectric sidewall spacers and from below by a PN junction. For example, in a trench-gated MOSFET the field shield region m... | 01/29/2008 |
| 7314791 | Bipolar transistor for an integrated circuit having variable value emitter ballast resistors An integrated circuit including a bipolar transistor with improved forward second breakdown is disclosed. In one embodiment, the bipolar transistor includes a base, a collector, a plurality of emitter sections coupled to a common emitter and a ballast emitter for ea... | 01/01/2008 |
| 7302982 | Label applicator and system A label applicator including a support surface having a central area and curving downwardly from the central area. A post assembly extends up from the central area such that a label having a label through-hole can be positioned in a support position generally on the... | 12/04/2007 |
| 7304354 | Buried guard ring and radiation hardened isolation structures and fabrication methods Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include the one or more parasitic isol... | 12/04/2007 |
| 7303968 | Semiconductor device and method having multiple subcollectors formed on a common wafer A semiconductor device and a method of fabricating a semiconductor device having multiple subcollectors which are formed in a common wafer, in order to provide multiple structures having different characteristic and frequency response are provided. The subcollectors... | 12/04/2007 |
| 7303970 | Method of fabricating dielectric mixed layers and capacitive element and use thereof The present invention provides a method for fabricating a capacitive element (100), a substrate (101) being provided as a first electrode layer of the capacitive element (100), the substrate (101) provided as an electrode layer is conditi... | 12/04/2007 |
| 7285830 | Lateral bipolar junction transistor in CMOS flow An improved lateral bipolar junction transistor and a method of forming such a lateral bipolar transistor without added mask in CMOS flow on a p-substrate are disclosed. The CMOS flow includes patterning and n-well implants; pattern and implant pocket implants for c... | 10/23/2007 |
| 7285455 | Method of producing the same A method of producing a semiconductor device includes the steps of: preparing a double SOI substrate, forming a deep trench, filling the deep trench, forming an opening, forming a cavity, depositing a polycrystalline silicon layer, and forming a bipolar transistor. | 10/23/2007 |
| 7282418 | Method for fabricating a self-aligned bipolar transistor without spacers According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises a sacrificial post situated on the top surface of the base. The bipolar transistor also comprises a conformal layer situated o... | 10/16/2007 |
| 7282771 | Structure and method for latchup suppression A method and structure for an integrated circuit comprising a substrate of a first polarity, a merged triple well region of a second polarity and a doped region of the second polarity abutting the well region. The doped region is adapted to suppress latch-up in the ... | 10/16/2007 |
| 7271070 | Method for producing transistors The invention relates to a method for producing integrable semiconductor components, especially transistors or logic gates, using a p-doped semiconductor substrate. First of all, a mask is applied to the semiconductor substrate in order to define a window that is de... | 09/18/2007 |
| 7265024 | DMOS device having a trenched bus structure A DMOS device having a trench bus structure thereof is introduced. The trench bus structure comprises a field oxide layer formed on a P substrate, and a trench extending from an top surface of the field oxide layer down to a lower portion of the P substrate. A gate ... | 09/04/2007 |
| 7262485 | Substrate for growing electro-optical single crystal thin film and method of manufacturing the same A substrate 1 for growing an electro-optical single crystal thin film in which two or more layers of buffer layers 3, 4, and 5 for buffering lattice mismatch between Si and BTO are formed on an Si (001) substrate 2 is provided as a substr... | 08/28/2007 |
| 7247899 | Semiconductor device, photoelectric conversion device and method of manufacturing same In a photoelectric conversion device having a buried layer in a part of an anode and a cathode of a photodiode, such as a CCD having a sensor structure and a CMOS sensor, well of the same conduction type as the conduction type of the buried layer can be disposed in ... | 07/24/2007 |
| 7247925 | Semiconductor device and method for fabricating the same A semiconductor device includes a semiconductor substrate of a first conductive type, a collector layer formed on the semiconductor substrate and made of a first semiconductor being of the first conductive type and having a higher resistance than that of the semicon... | 07/24/2007 |
| 7242012 | Lithography device for semiconductor circuit pattern generator General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor ... | 07/10/2007 |
| 7242061 | Semiconductor device The invention provides semiconductor devices having an output circuit in which transistors do not fail to achieve their original capability, and electrostatic breakdown is difficult to occur. A semiconductor device is equipped with a semiconductor substrate, an elem... | 07/10/2007 |
| 7226844 | Method of manufacturing a bipolar transistor with a single-crystal base contact A method forms a bipolar transistor in a semiconductor substrate of a first conductivity type. The method includes: forming on the substrate a single-crystal silicon-germanium layer; forming a heavily-doped single-crystal silicon layer of a second conductivity type;... | 06/05/2007 |
| 7226504 | Method to form thick relaxed SiGe layer with trench structure A method of forming a SiGe layer having a relatively high germanium content and a relatively low threading dislocation density includes preparing a silicon substrate; depositing a layer of SiGe to a thickness of between about 100 nm to 500 nm, wherein the germanium ... | 06/05/2007 |
| 7226835 | Versatile system for optimizing current gain in bipolar transistor structures Disclosed are apparatus and methods for designing electrical contact for a bipolar emitter structure. The area of an emitter structure (106, 306, 400, 404) and the required current density throughput of an electrical contact structure (108, 308, 402, 406 | 06/05/2007 |
| 7223696 | Methods for maskless lithography General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor ... | 05/29/2007 |
| 7198998 | Method of manufacturing bipolar-complementary metal oxide semiconductor A method of manufacturing a bipolar-complementary metal oxide semiconductor (BiCMOS) is provided. A gate in a CMOS area and a conductive layer pattern defining an opening, which opens an active region in a bipolar transistor area, are simultaneously formed by patter... | 04/03/2007 |
| 7193239 | Three dimensional structure integrated circuit A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, red... | 03/20/2007 |
| 7192826 | Semiconductor device and process for fabrication thereof Disclosed is a semiconductor device in which the capacitive element of MIMC structure has a low parasitic capacity. A process for fabrication of said semiconductor device. The semiconductor device has a capacitive element of MIMC structure, a PN photodiode, and a ve... | 03/20/2007 |
