Quotables
"We are probably nearing the limit of all we can know about astronomy."
Simon Newcomb, astronomer ; 1888
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8124473 | Strain enhanced semiconductor devices and methods for their fabrication A strain enhanced semiconductor device and methods for its fabrication are provided. One method comprises embedding a strain inducing semiconductor material in the source and drain regions of the device to induce a strain in the device channel. Thin metal silicide c... | 02/28/2012 |
| 8084320 | Non-volatile memory and method for fabricating the same A non-volatile memory is described, which includes gate structures, doped regions, second spacers and contact plugs. The gate structures are disposed on the substrate, each of which includes a control gate and a gate dielectric layer. The control gates are disposed ... | 12/27/2011 |
| 7977182 | Method of manufacturing MISFET with low contact resistance Described herein is a method of manufacturing a semiconductor device realizing higher performance by reducing contact resistance of an electrode. In the method, a gate insulating film, a gate electrode are formed on a semiconductor substrate. A first metal is deposi... | 07/12/2011 |
| 7955925 | Method of manufacturing semiconductor device After gate insulating films, gate electrodes, and n+ type semiconductor regions and p+ type semiconductor regions for source/drain are formed, a metal film and a barrier film are formed on a semiconductor substrate. And a first heat treatment i... | 06/07/2011 |
| 7906390 | Thin gate electrode CMOS devices and methods of fabricating same A CMOS device and method of forming the CMOS device. The device including a source and a drain formed in a semiconductor substrate, the source and the drain and separated by a channel region of the substrate; a gate dielectric formed on a top surface of the substrat... | 03/15/2011 |
| 7838359 | Technique for forming contact insulation layers and silicide regions with different characteristics A technique is provided that enables the formation of metal silicide individually for N-channel transistors and P-channel transistors, while at the same time a strain-inducing mechanism is also provided individually for each transistor type. In this way, a cobalt si... | 11/23/2010 |
| 7772064 | Method of fabricating self-aligned contact A method of fabricating a self-aligned contact is provided. A first dielectric layer is formed on a substrate having a contact region thereon. Next, a lower opening corresponding to the contact region is formed in the first dielectric layer. Thereafter, a second die... | 08/10/2010 |
| 7723179 | Light emitting device and method for manufacturing the same A light emitting element containing an organic compound has a disadvantage in that it tends to be deteriorated by various factors, so that the greatest problem thereof is to increase its reliability (make longer its life span). The present invention provides a metho... | 05/25/2010 |
| 7678642 | Method for manufacturing phase change memory device using a patterning process A phase change memory device is made by processes including forming a first interlayer dielectric on a semiconductor substrate that has junction regions. Then etching the first interlayer dielectric and thereby defining contact holes that expose the junction regions... | 03/16/2010 |
| 7670896 | Method and structure for reducing floating body effects in MOSFET devices A field effect transistor (FET) device includes a bulk substrate, a gate insulating layer formed over the bulk substrate, source and drain regions formed in an active device area associated with the bulk substrate, the source and drain regions each defining a p/n ju... | 03/02/2010 |
| 7572694 | Method of manufacturing a semiconductor device A method for manufacturing a semiconductor device includes forming an insulation film over a semiconductor substrate having a conduction layer; forming a trench pattern over the insulation film; etching an upper portion of the insulation film by using the trench pat... | 08/11/2009 |
| 7547597 | Direct alignment scheme between multiple lithography layers A method for directly aligning multiple lithography masking layers. The method may be used to fabricate a flash plus logic structure. The flash plus logic structure may comprise a flash memory cell, a logic cell and a transistor. ... | 06/16/2009 |
| 7514314 | Method of manufacturing semiconductor device and semiconductor memory device A method of manufacturing a semiconductor device includes: (A) forming a gate electrode of a transistor on a substrate, a top layer of the gate electrode being a first metal film; (B) blanket depositing an interlayer insulating film; and (C) forming a first contact ... | 04/07/2009 |
| 7504296 | Semiconductor memory device and method for fabricating the same The present invention relates to a semiconductor memory device and a method for fabricating the same. The semiconductor memory device, including: a plurality of gate structures formed on a substrate; a contact junction region formed beneath the substrate disposed in... | 03/17/2009 |
| 7498218 | Semiconductor device with low contact resistance and method for fabricating the same A semiconductor device with a low contact resistance and a method for fabricating it are described. The semiconductor device includes a substrate structure with a contact hole and a contact plug formed on the contact hole. The contact plug is provided with an epitax... | 03/03/2009 |
| 7476584 | Method of fabricating a semiconductor device with a bit line contact plug In one embodiment, a semiconductor device includes a plurality of gate electrodes formed on a semiconductor substrate including a cell region, a core region, and a peripheral circuit region, along with source/drain regions. A first landing pad contacts the source/dr... | 01/13/2009 |
| 7465624 | Method of manufacturing semiconductor device The present invention provides a method of manufacturing a semiconductor device, comprising forming an electrode pattern made of silicon on a gate insulating film in an n-MOS region and a p-MOS region of a semiconductor substrate, masking the n-MOS region including ... | 12/16/2008 |
| 7427544 | Semiconductor device and method of manufacturing the same A semiconductor device includes an element isolation insulating film provided in a semiconductor substrate between first and second element regions, a gate electrode running over the element isolation insulating film, first and second element regions, a first stoppe... | 09/23/2008 |
| 7402485 | Method of forming a semiconductor device A sidewall spacer structure is formed adjacent to a gate structure whereby a material forming an outer surface of the sidewall spacer structure contains nitrogen. Subsequent to its formation the sidewall spacer structure is annealed to harden the sidewall spacer str... | 07/22/2008 |
| 7396718 | Technique for creating different mechanical strain in different channel regions by forming an etch stop layer stack having differently modified intrinsic stress A technique is provided that allows the formation of contact etch stop layers having different intrinsic stress for different transistors, while substantially avoiding any device degradation owing to the partial removal of the contact etch stop layer. Hereby, an add... | 07/08/2008 |
| 7390719 | Method of manufacturing a semiconductor device having a dual gate structure A semiconductor device having a dual gate is formed on a substrate having a dielectric layer. A first metallic conductive layer is formed on the dielectric layer to a first thickness, and annealed to have a reduced etching rate. A second metallic conductive layer is... | 06/24/2008 |
| 7382054 | Method for forming self-aligned contacts and local interconnects simultaneously The present invention relates generally to semiconductors, and more specifically to semiconductor memory device structures and an improved fabrication process for making the same. The improved fabrication process allows the self-aligned contacts and local interconne... | 06/03/2008 |
| 7381610 | Semiconductor transistors with contact holes close to gates A structure and a method for forming the same. The structure includes (a) a semiconductor layer including a channel region disposed between first and second S/D regions; (b) a gate dielectric region on the channel region; (c) a gate region on the gate dielectric reg... | 06/03/2008 |
| 7371634 | Amorphous carbon contact film for contact hole etch process A semiconductor device including a contact etch stop layer and contact hole formation method for reduced underlying material loss and improved device performance, the method including providing a semiconductor substrate including an active region including a CMOS de... | 05/13/2008 |
| 7368342 | Semiconductor device and method of manufacturing the same A method for manufacturing a semiconductor device includes forming a gate-insulating film on a semiconductor substrate; forming a gate electrode on the gate-insulating film to be electrically insulated from the semiconductor substrate; etching the gate electrode, th... | 05/06/2008 |
| 7368775 | Single transistor DRAM cell with reduced current leakage and method of manufacture A single transistor planar DRAM memory cell with improved charge retention and reduced current leakage and a method for forming the same, the method including providing a semiconductor substrate; forming a gate dielectric on the semiconductor substrate; forming a pa... | 05/06/2008 |
| 7361932 | Semiconductor device and method for fabricating the same A semiconductor device of a dual-gate structure including a P-channel type field-effect transistor formed at a first region of a substrate and an N-channel type field-effect transistor formed at a second region of the substrate, includes a gate electrode including a... | 04/22/2008 |
| 7358595 | Method for manufacturing MOS transistor Disclosed is a method for fabricating a MOS transistor. The present method includes forming a buffer layer pattern including nitrogen on the semiconductor substrate; forming a gate insulating layer and a gate electrode on the exposed substrate surface; forming a LDD... | 04/15/2008 |
| 7355254 | Pinning layer for low resistivity N-type source drain ohmic contacts A system or apparatus including an N-type transistor structure including a gate electrode formed on a substrate and source and drain regions formed in the substrate; a contact to the source region; and a pinning layer disposed between the source region and the first... | 04/08/2008 |
| 7354819 | Method of manufacturing CMOS with silicide contacts A semiconductor device is disclosed, which comprises a silicon substrate, a complementary MISFET circuit, an insulation film formed on the silicon substrate, a first contact hole formed in the insulation film, a first metal silicide layer formed on the bottom of the... | 04/08/2008 |
| 7355895 | Nonvolatile semiconductor memory and driving method the same A nonvolatile semiconductor memory includes a memory cell array, a control circuit and an address control circuit. In the memory cell array, a plurality of memory cells are arranged in a matrix of rows and columns. The control circuit sets a write/erase mode in resp... | 04/08/2008 |
| 7351630 | Method of manufacturing flash memory device A method of manufacturing a flash memory device, including the steps of forming a gate on a semiconductor substrate in which a cell region, a source selection line region, and a drain selection line region are defined and then forming spacers on sidewalls of the gat... | 04/01/2008 |
| 7341931 | Methods of forming low resistivity contact for an integrated circuit device Contact areas comprising doped semiconductor material at the bottom of contact holes are cleaned in a hot hydrogen plasma and exposed in situ during and/or separately from the hot hydrogen clean to a plasma containing the same dopant species as in the semiconductor ... | 03/11/2008 |
| 7342289 | Strained silicon MOS devices A structure to improve carrier mobility of a MOS device in an integrated circuit. The structure comprises a semiconductor substrate, containing a source region and a drain region; a conductive gate overlying a gate dielectric layer on the semiconductor substrate; a ... | 03/11/2008 |
| 7332418 | High-density single transistor vertical memory gain cell A memory cell which is formed on a substrate of a first conductivity type. A pillar of the first conductivity type extends vertically upward from the substrate. A source region of a second conductivity type is formed in the substrate extending adjacent to and away f... | 02/19/2008 |
| 7326606 | Semiconductor processing methods In one aspect, the invention provides a method of forming a contact opening to a conductive line. In one preferred implementation, a contact opening is formed to a conductive line which overlies a substrate isolation area with an etch which also outwardly exposes su... | 02/05/2008 |
| 7323391 | Substrate having silicon germanium material and stressed silicon nitride layer A method of fabricating a semiconductor device includes providing a region having doped silicon region on a substrate, and forming a silicon germanium material adjacent to the region on the substrate. A stressed silicon nitride layer is formed over at least a portio... | 01/29/2008 |
| 7307008 | Methods of forming integrated circuit devices including a multi-layer poly film cell pad contact hole Methods of forming a cell pad contact hole on an integrated circuit include forming adjacent gates on an integrated circuit substrate having a source/drain region extending between the gates. Gate spacers are formed on facing sidewalls of the adjacent gates. A cell ... | 12/11/2007 |
| 7303952 | Method for fabricating doped polysilicon lines A method of fabricating polysilicon lines and polysilicon gates, the method of including: providing a substrate; forming a dielectric layer on a top surface of the substrate; forming a polysilicon layer on a top surface of the dielectric layer; implanting the polysi... | 12/04/2007 |
| 7291895 | Integrated circuitry A silicon nitride comprising layer formed over a semiconductor substrate includes Al, Ga or a mixture thereof. A silicon dioxide comprising layer is formed proximate thereto. The silicon dioxide comprising layer is removed substantially selectively relative to the s... | 11/06/2007 |
