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| Number | Title | Issue Date |
| 8173504 | Method of fabricating gate electrode using a treated hard mask A method for fabricating an integrated device is disclosed. A polysilicon gate electrode layer is provided on a substrate. In an embodiment, a treatment is provided on the polysilicon gate electrode layer to introduce species in the gate electrode layer and form an ... | 05/08/2012 |
| 7932144 | Semiconductor structure and method of forming the structure Disclosed are embodiments of an n-FET structure with silicon carbon S/D regions completely contained inside amorphization regions and with a carbon-free gate electrode. Containing carbon within the amorphization regions, ensures that all of the carbon is substitutio... | 04/26/2011 |
| 7871880 | Method for manufacturing electronic devices integrated in a semiconductor substrate and corresponding devices A method manufactures a vertical power MOS transistor on a semiconductor substrate comprising a first superficial semiconductor layer of a first conductivity type, comprising: forming trench regions in the first semiconductor layer, filling in said trench regions wi... | 01/18/2011 |
| 7776681 | Semiconductor device and method for manufacturing the same A first resist mask and a second resist mask used for forming a gate electrode for a p-channel TFT and a gate electrode for an n-channel TFT are left, and a third resist mask is formed afterwards over a first area where one of the p-channel TFT and the n-channel TFT... | 08/17/2010 |
| 7704823 | Strained semiconductor device and method of making same To form a semiconductor device, an electrode layer is formed over a semiconductor body. The electrode layer includes an amorphous portion. A liner, e.g., a stress-inducing liner, is deposited over the electrode layer. The electrode layer is annealed to recrystallize... | 04/27/2010 |
| 7645665 | Semiconductor device having shallow b-doped region and its manufacture A method for manufacturing a semiconductor device has the steps of: (a) implanting boron (B) ions into a semiconductor substrate; (b) implanting fluorine (F) or nitrogen (N) ions into the semiconductor device; (c) after the steps (a) and (b) are performed, executing... | 01/12/2010 |
| 7611943 | Transistors, integrated circuits, systems, and processes of manufacture with improved work function modulation A process (200) for making integrated circuits with a gate, uses a doped precursor (124, 126N and/or 126P) on barrier material (118) on gate dielectric (116). The process (200) involves totally consuming (271) the dop... | 11/03/2009 |
| 7544561 | Electron mobility enhancement for MOS devices with nitrided polysilicon re-oxidation A semiconductor structure includes a PMOS device and an NMOS device. The PMOS device includes a first gate dielectric on a semiconductor substrate, a first gate electrode on the first gate dielectric, and a first gate spacer along sidewalls of the first gate electro... | 06/09/2009 |
| 7504295 | Methods for fabricating dynamic random access memory cells having laterally offset storage nodes DRAM cells include a common drain region in an integrated circuit substrate and first and second source regions in the integrated circuit substrate, a respective one of which is laterally offset from the common drain region along respective first and second opposite... | 03/17/2009 |
| 7432144 | Method for forming a transistor for reducing a channel length A method of forming a transistor including: forming a gate oxide layer pattern and gate polysilicon layer pattern on a silicon substrate; forming a low energy ion implantation region aligned with both sidewalls of the gate polysilicon layer pattern; forming an amorp... | 10/07/2008 |
| 7419863 | Fabrication of semiconductor structure in which complementary field-effect transistors each have hypoabrupt body dopant distribution below at least one source/drain zone Complementary IGFETs (210W and 220W or 530 and 540) are fabricated so that the body dopant concentration in each IGFET decreases by at least 10 in moving from a subsurface location in the body material of that IGFET up to one of it... | 09/02/2008 |
| 7419867 | CMOS gate structure comprising predoped semiconductor gate material with improved uniformity of dopant distribution and method of forming the structure By predoping of a layer of deposited semiconductor gate material by incorporating dopants during the deposition process, a high uniformity of the dopant distribution may be achieved in the gate electrodes of CMOS devices subsequently formed in the layer of gate mate... | 09/02/2008 |
| 7402485 | Method of forming a semiconductor device A sidewall spacer structure is formed adjacent to a gate structure whereby a material forming an outer surface of the sidewall spacer structure contains nitrogen. Subsequent to its formation the sidewall spacer structure is annealed to harden the sidewall spacer str... | 07/22/2008 |
| 7399670 | Methods of forming different gate structures in NMOS and PMOS regions and gate structures so formed A method of forming transistor gate structures in an integrated circuit device can include forming a high-k gate insulating layer on a substrate including a first region to include PMOS transistors and a second region to include NMOS transistors. A polysilicon gate ... | 07/15/2008 |
| 7396717 | Method of forming a MOS transistor A method of forming a MOS transistor, in which a co-implantation is performed to implant an implant into a source region and a drain region or a halo implanted region to effectively prevent dopants from over diffusion in the source region and the drain region or the... | 07/08/2008 |
| 7390719 | Method of manufacturing a semiconductor device having a dual gate structure A semiconductor device having a dual gate is formed on a substrate having a dielectric layer. A first metallic conductive layer is formed on the dielectric layer to a first thickness, and annealed to have a reduced etching rate. A second metallic conductive layer is... | 06/24/2008 |
| 7364972 | Semiconductor device A semiconductor device comprises a semiconductor substrate, a first circuit formed on the substrate, and a second circuit connected to the first circuit as an input/output portion thereof and powered by a voltage higher than that for the first circuit, the first cir... | 04/29/2008 |
| 7364997 | Methods of forming integrated circuitry and methods of forming local interconnects In one implementation, field oxide is grown within bulk semiconductive material in a first circuitry area and not over immediately adjacent bulk semiconductive material in a second circuitry area. The field oxide is etched from the first circuitry area. After the et... | 04/29/2008 |
| 7364995 | Method of forming reduced short channel field effect transistor A method for manufacturing a semiconductor device capable of reducing a short channel effect, whereby the semiconductor device includes a pair of impurity regions for a source and a drain formed on a semiconductor substrate, a gate having a gate electrode used to co... | 04/29/2008 |
| 7358131 | Methods of forming SRAM constructions The invention includes SRAM constructions comprising at least one transistor device having an active region extending into a crystalline layer comprising Si/Ge. A majority of the active region within the crystalline layer is within a single crystal of the crystallin... | 04/15/2008 |
| 7338865 | Method for manufacturing dual work function gate electrodes through local thickness-limited silicidation The present invention provides a method of manufacturing a semiconductor device. The semiconductor device (100), among other possible elements, includes a first transistor (120) located over a semiconductor substrate (110), wherein the first tra... | 03/04/2008 |
| 7335911 | Semiconductor device and manufacturing method thereof By providing appropriate TFT structures arranged in various circuits of the semiconductor device in response to the functions required by the circuits, it is made possible to improve the operating performances and the reliability of a semiconductor device, reduce po... | 02/26/2008 |
| 7332433 | Methods of modulating the work functions of film layers Methods for fabricating two metal gate stacks with varying work functions for complementary metal oxide semiconductor (CMOS) devices are provided A first metal layer may be deposited onto a gate dielectric, followed by the deposition of a second metal layer, where t... | 02/19/2008 |
| 7332389 | Selective polysilicon stud growth A memory cell having a bit line contact is provided. The memory cell may be a 6F2 memory cell. The bit line contact may have a contact hole bounded by insulating sidewalls, and the contact hole may be partially or completely filled with a doped polysilico... | 02/19/2008 |
| 7329570 | Method for manufacturing a semiconductor device An exemplary method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a P-well and an N-well for high voltage (HV) devices and a first well in a low voltage/medium voltage (LV/MV) region for a logic device, ... | 02/12/2008 |
| 7326601 | Methods for fabrication of a stressed MOS device Methods for fabricating a stressed MOS device is provided. One method comprises the steps of providing a monocrystalline semiconductor substrate having a surface and a channel abutting the surface. A gate electrode having a first edge and a second edge is formed ove... | 02/05/2008 |
| 7326606 | Semiconductor processing methods In one aspect, the invention provides a method of forming a contact opening to a conductive line. In one preferred implementation, a contact opening is formed to a conductive line which overlies a substrate isolation area with an etch which also outwardly exposes su... | 02/05/2008 |
| 7314803 | Method for producing a semiconductor structure In a method for producing a semiconductor structure a semiconductor a substrate with a top surface is provided. A gate dielectric layer is provided on the top surface and on the gate dielectric layer is provided a memory cell array region with a first plurality of g... | 01/01/2008 |
| 7314805 | Method for fabricating semiconductor device An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of ... | 01/01/2008 |
| 7309636 | High-voltage metal-oxide-semiconductor device and method of manufacturing the same The present invention pertains to a high-voltage MOS device. The high-voltage MOS device includes a substrate, a first well, a first field oxide layer enclosing a drain region, a second field oxide enclosing a source region, and a third field oxide layer encompassin... | 12/18/2007 |
| 7300839 | Selective polysilicon stud growth A memory cell having a bit line contact is provided. The memory cell may be a 6F2 memory cell. The bit line contact may have a contact hole bounded by insulating sidewalls, and the contact hole may be partially or completely filled with a doped polysilico... | 11/27/2007 |
| 7294875 | Nanoscale programmable structures and methods of forming and using same A programmable structure and device and methods of forming and using the structure and device are disclosed. The structure includes a soluble electrode, an ion conductor, and an inert electrode. Upon application of a sufficient voltage, a conductive region forms wit... | 11/13/2007 |
| 7285449 | Semiconductor device manufacture method including process of implanting impurity into gate electrode independently from source /drain and semiconductor device manufactured by the method A gate electrode made of semiconductor is formed on the partial surface area of a semiconductor substrate. A mask member is formed on the surface of the semiconductor substrate in an area adjacent to the gate electrode. Impurities are implanted into the gate electro... | 10/23/2007 |
| 7282403 | Temperature stable metal nitride gate electrode An integrated circuit is provided including an FET gate structure formed on a substrate. This structure includes a gate dielectric on the substrate, and a metal nitride layer overlying the gate dielectric and in contact therewith. This metal nitride layer is charact... | 10/16/2007 |
| 7276407 | Method for fabricating semiconductor device A method for fabricating a semiconductor device including on a single semiconductor substrate, a first MOS transistor having a first gate insulating film of a predetermined thickness, and second and third MOS transistors sharing a second gate insulating film smaller... | 10/02/2007 |
| 7265011 | Method of manufacturing a transistor A method of manufacturing a transistor according to some embodiments includes sequentially forming a dummy gate oxide layer and a dummy gate electrode on an active region of a semiconductor substrate, ion-implanting a first conductive impurity into source/drain regi... | 09/04/2007 |
| 7259054 | Method of manufacturing a semiconductor device that includes a process for forming a high breakdown voltage field effect transistor With the objective of suppressing or preventing a kink effect in the operation of a semiconductor device having a high breakdown voltage field effect transistor, n+ type semiconductor regions, each having a conduction type opposite to p+ type s... | 08/21/2007 |
| 7259431 | Static random access memory using thin film transistors A semiconductor thin film is formed having a lateral growth region which is a collection of columnar or needle-like crystals extending generally parallel with a substrate. The semiconductor thin film is illuminated with laser light or strong light having equivalent ... | 08/21/2007 |
| 7253049 | Method for fabricating dual work function metal gates A method for making PMOS and NMOS transistors 60, 70 on a semiconductor substrate 20 that includes having a gate protection layer 210 over the gate electrode layer 110 during the formation of source/drain silicides 120. The method ... | 08/07/2007 |
| 7253052 | Method for forming a storage cell capacitor compatible with high dielectric constant materials Described are integrated circuit electrodes and method for fabricating an electrode, which include, in an embodiment forming a silicon, first portion of the electrode in a lower region of a substrate opening. The method may further include forming a second portion o... | 08/07/2007 |
