Class 438/231 - Plural doping steps

Subclass of Class 438 - Semiconductor device manufacturing: process
Definition: Process including multiple steps of introducing electrically
No. of patents: 763
Last issue date: 05/08/2012

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Number	Title	Issue Date
6395571	Method for fabricating polysilicon TFT Fabrication of a polysilicon TFT having a lightly doped drain or offset structure. Fabrication includes forming a semiconductor layer, a gate insulating film, and a gate electrode on a substrate. Then, forming lightly doped impurity regions in the semicon...	05/28/2002
6391702	Method of manufacture for semiconductor devices A method of manufacturing a semiconductor device that can limit etch damage is disclosed. According to one embodiment, isolation regions (102) may be formed in a substrate (101). A word line (103) may be formed in a first region. A protective film (105) m...	05/21/2002
6388288	Integrating dual supply voltages using a single extra mask level Integration of dual voltages on a single chip can be accomplished with a minimum of extra masks by optimizing only the MDD implant of the peripheral transistors, while other implants remain the same for both transistor types. This meets lifetime specifica...	05/14/2002
6372590	Method for making transistor having reduced series resistance A transistor having reduced series resistance and method for producing the same. The method reduces transistor series resistance by implanting nitrogen into an nLDD/Source/Drain extension region of the transistor. The nitrogen implantation in connection w...	04/16/2002
6368927	Method of manufacturing transistor having elevated source and drain regions A method of manufacturing a transistor having an elevated drain in a substrate includes the steps of: forming a gate structure on the substrate; providing a first doped region adjacent to one end of the gate structure, the first doped region having a firs...	04/09/2002
6365450	Fabrication of P-channel field effect transistor with minimized degradation of metal oxide gate For fabricating a PMOS (P-channel Metal Oxide Semiconductor) field effect transistor on a semiconductor substrate, a PMOS gate dielectric is formed on the semiconductor substrate, and a PMOS dummy gate electrode is formed on the gate dielectric. A P-type ...	04/02/2002
6365496	Elimination of junction spiking using soft sputter etch and two step tin film during the contact barrier deposition process A contact opening to a silicon substrate within which a metal contact is to be formed is cleaned by soft sputter etch to clean the substrate surface and remove any residue which would interfere with formation of a continuous silicide layer across the cont...	04/02/2002
6362035	Channel stop ion implantation method for CMOS integrated circuits A method for incorporating an ion implanted channel stop layer under field isolation for a twin-well CMOS process is described in which the layer is placed directly under the completed field isolation by a blanket boron ion implant over the whole wafer. T...	03/26/2002
6358787	Method of forming CMOS integrated circuitry A method of forming CMOS integrated circuitry includes, a) providing a series of gate lines over a semiconductor substrate, a first gate line being positioned relative to an area of the substrate for formation of an NMOS transistor, a second gate line bei...	03/19/2002
6350639	Simplified graded LDD transistor using controlled polysilicon gate profile An ultra-large scale CMOS integrated circuit semiconductor device with LDD structures is manufactured by forming a gate oxide layer over the semiconductor substrate; forming a polysilicon layer over the gate oxide layer; forming a first mask layer over th...	02/26/2002
6346439	Semiconductor transistor devices and methods for forming semiconductor transistor devices The invention includes a method for forming graded junction regions comprising: a) providing a semiconductor material wafer; b) providing a transistor gate over the semiconductor material wafer, the transistor gate having opposing lateral sidewalls; c) pr...	02/12/2002
6344381	Method for forming pillar CMOS A method of forming a pillar CMOS FET device, especially an inverter, and the device so formed is provided. The method includes forming abutting N wells and P wells in a silicon substrate and then forming N+ and P+ diffusions in the ...	02/05/2002
6335252	Semiconductor device manufacturing method An MIS transistor manufacturing method which can prevent unwanted diffusion of extensions caused by the drive to the source/drain so that the diffusion of the source/drain and the diffusion of the extensions can independently be controlled so as to obtain...	01/01/2002
6333249	Method for fabricating a semiconductor device A method for fabricating a semiconductor device is disclosed. In a process for fabricating a CMOS transistor of a high integrated semiconductor device and a cell of a DRAM, a process for forming a dual gate electrode having a layered structure of a tungst...	12/25/2001
6333244	CMOS fabrication process with differential rapid thermal anneal scheme A method of fabricating an integrated circuit with ultra-shallow source/drain junctions utilizes a dual amorphization technique. The technique creates a shallow amorphous region and a deep amorphous region. The shallow amorphous region is between 10-15 nm...	12/25/2001
6331458	Active region implant methodology using indium to enhance short channel performance of a surface channel PMOS device An MOS device is provided using indium as a threshold adjust implant in the channel regions of an NMOS device and/or in the conductive gate overlying the channel region in a PMOS device. Indium ions are relatively immobile and achieve location stability i...	12/18/2001
6331493	Process for making low dielectric constant dielectric films A low dielectric constant material and a process for controllably reducing the dielectric constant of a layer of such material is provided and comprises the step of exposing the layer of dielectric material to a concentration of an oxygen plasma at a temp...	12/18/2001
6326664	Transistor with ultra shallow tip and method of fabrication A novel transistor with a low resistance ultra shallow tip region and its method of fabrication. The novel transistor of the present invention has a source/drain extension or tip comprising an ultra shallow region which extends beneath the gate electrode ...	12/04/2001
6326250	Semiconductor processing method of fabricating field effect transistors In one aspect of the invention, a semiconductor processing method includes: a) providing a semiconductor substrate; b) defining a first conductivity type region and a second conductivity type region of the semiconductor substrate; c) providing a first tra...	12/04/2001
6323077	Inverse source/drain process using disposable sidewall spacer The present invention discloses an inverse source/drain process using disposable sidewall, for forming an LDD MOSFET device on a semiconductor substrate, comprises the following steps: forming a gate electrode on the semiconductor substrate; forming a dis...	11/27/2001
6323091	Method of forming semiconductor memory device with LDD A method for manufacturing a semiconductor device in which ROM programming ion implantation is performed by utilizing the same mask as used for implanting dopant in MOS transistors. The ROM programming ion implantation is conducted under the same conditio...	11/27/2001
6319762	Method for fabricating poly-spacers A method for fabricating poly-spacers used in a semiconductor substrate, comprising: forming an undoped first polysilicon layer on the semiconductor substrate; performing a first ion implantation with a first angle to implant impurities into the first pol...	11/20/2001
6316303	Method of fabricating a MOS transistor having SEG silicon A method of fabricating a MOS transistor having SEG Si. After the formation of a gate and a spacer and before a source/drain region is formed, a selective epitaxial growth (SEG) Si is deposited over the substrate. The spacer is then removed to form an ult...	11/13/2001
6313020	Semiconductor device and method for fabricating the same The present invention provides a semiconductor device and a method for fabricating the same. In the present invention, an electron depletion preventing layer is formed in a bottom portion of a polysilicon gate of MOSFET devices. In addition, the ion-impla...	11/06/2001
6309935	Methods of forming field effect transistors Methods of forming field effect transistors. In one aspect, a method of forming a field effect transistor includes: a) providing a gate structure over a semiconductor substrate, the gate structure comprising a conductively-doped polysilicon region and a d...	10/30/2001
6309921	Semiconductor device and method for fabricating semiconductor device The semiconductor device comprises a semiconductor substrate 10 of a first conduction-type, first wells 20a, 20b of a second conduction-type formed in a first region on the primary surface of the semiconductor substrate 10, a second well 22a formed in a s...	10/30/2001
6309936	Integrated formation of LDD and non-LDD semiconductor devices A method of forming a semiconductor device includes forming a first gate electrode over a substrate and then forming a spacer on at least one sidewall of the first gate electrode. A second gate electrode is formed over the substrate after forming the spac...	10/30/2001
6306712	Sidewall process and method of implantation for improved CMOS with benefit of low CGD, improved doping profiles, and insensitivity to chemical processing A transistor (30) and method for forming a transistor using an edge blocking material (24) is disclosed herein. The edge blocking material (24) may be located adjacent a gate (22) or disposable gate or may be part of a disposable gate. During an angled po...	10/23/2001
6306702	Dual spacer method of forming CMOS transistors with substantially the same sub 0.25 micron gate length CMOS transistors, i.e., N- and P-type transistors, are formed with substantially the same gate length and source/drain regions with lightly doped extensions. Embodiments include sequentially: ion implanting an N-type impurity, e.g. As, to form the N- type...	10/23/2001
6306701	Self-aligned contact process A self-aligned contact process. A substrate is provided. A gate including a polysilicon layer and a metal silicide layer is formed on the substrate. A cap layer is formed on the gate to protect the gate. A first spacer is formed on the sidewall of the gat...	10/23/2001
6303418	Method of fabricating CMOS devices featuring dual gate structures and a high dielectric constant gate insulator layer A method of forming a metal gate structure, on a high k gate insulator layer, for NMOS devices, and simultaneously forming a metal-polysilicon gate structure, on the same high k gate insulator layer, for PMOS devices, has been developed. The method featur...	10/16/2001
6300656	Nonvolatile semiconductor memory device having a drain region of different impurity density and conductivity types A nonvolatile semiconductor memory device includes an n-type region which is in contact with n+ drain diffusion region at a surface of p-type silicon substrate and covers the periphery thereof. The device also includes a p-type impurity region ...	10/09/2001
6294416	Method of fabricating CMOS transistors with self-aligned planarization twin-well by using fewer mask counts The present invention discloses a method of forming CMOS transistors with self-aligned planarization twin-well by using fewer mask counts. After a silicon nitride layer is formed over a first pad oxide layer on a semiconductor substrate, an N-well region ...	09/25/2001
6291278	Method of forming transistors with self aligned damascene gate contact A method of fabricating a transistor having shallow source and drain extensions utilizes a self-aligned contact. The drain extensions are provided through an opening between a contact area and the gate structure. A high-K gate dielectric material can be u...	09/18/2001
6291280	CMOS imager cell having a buried contact and method of fabrication An imaging device formed as a CMOS semiconductor integrated circuit includes a buried contact between the floating diffusion region and the gate of a source follower output transistor. The buried contact in the CMOS imager decreases leakage from the diffu...	09/18/2001
6291284	Method of fabricating semiconductor device This invention provides a semiconductor device such as an MOS transistor and a method of fabricating the same wherein a field oxide film is provided to surround a device region of a semiconductor substrate (including well), providing a gate on the device ...	09/18/2001
6287906	Semiconductor device having MOS transistor and method of manufacturing the same An MOS transistor capable of improving hot carrier resistance and a method of manufacturing thereof are provided. In the MOS transistor, nitrogen is introduced in a sidewall oxide film, so that a concentration distribution of nitrogen in a section perpend...	09/11/2001
6281058	Method of forming DRAM circuitry on a semiconductor substrate A method of forming DRAM circuitry includes, a) defining a memory array area on a substrate for formation of first conductivity type DRAM field effect transistors and defining an area peripheral to the array on the substrate for formation of second conduc...	08/28/2001
6282459	Structure and method for detection of physical interference during transport of an article A method for detecting physical interference with desired transport of an article. The method includes the step of detecting an operative acoustic signal representing the structure-borne sound pattern of an article during said article transport, and detec...	08/28/2001
6277682	Source drain implant process for mixed voltage CMOS devices A mixed voltage CMOS process for fabricating transistors with different source-drain profiles is described. The present invention comprises a method for manufacturing a CMOS integrated circuit with a low voltage device 24 and a high voltage device 26 comp...	08/21/2001

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Class 438/231 - Plural doping steps