Class 438/231 - Plural doping steps

Subclass of Class 438 - Semiconductor device manufacturing: process
Definition: Process including multiple steps of introducing electrically
No. of patents: 747
Last issue date: 02/23/2010

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Number	Title	Issue Date
7666736	Method for fabricating semiconductor device comprising P-type MISFET, including step of implanting fluorine After the implantation of fluorine ions into a semiconductor substrate, a gate insulating film, a gate electrode and a protective film are formed on the semiconductor substrate. Thereafter, fluorine ions are again implanted into the semiconductor substrate. Furtherm...	02/23/2010
7629216	Method for fabricating CMOS image sensor with plasma damage-free photodiode A method for fabricating a complementary metal-oxide semiconductor (CMOS) image sensor includes providing a semi-finished substrate, forming a patterned blocking layer over a photodiode region of the substrate, implanting impurities on regions other than the photodi...	12/08/2009
7601583	Transistor structure of memory device and method for fabricating the same A memory device includes an active area protruding from a semiconductor substrate. A recess is formed in the active area. A field oxide layer is formed on the semiconductor substrate. A gate electrode extends across the active area while being overlapped with the re...	10/13/2009
7582523	Method of manufacturing semiconductor device including insulated-gate field-effect transistors A method of manufacturing a semiconductor device including MOS transistors is disclosed. N-type and p-type semiconductor films are formed respectively above first and second surface regions of a semiconductor substrate. First and second protective films are laminate...	09/01/2009
7494862	Methods for uniform doping of non-planar transistor structures Methods for uniformly tip doping a silicon body of a non-planar transistor and devices and systems formed by such methods. In one embodiment, a method can include vertical tip ion implantation of a silicon body with at least three surfaces on a substrate followed by...	02/24/2009
7473595	Method for decreasing PN junction leakage current of dynamic random access memory A method for decreasing a PN junction leakage current of a dynamic random access memory (DRAM), including the steps of: preparing an NMOS transistor formed on a P-type silicon substrate and comprising a drain; forming an insulation oxide layer on the P-type silicon ...	01/06/2009
7456062	Method of forming a semiconductor device A sidewall spacer structure is formed adjacent to a gate structure whereby a material forming an outer surface of the sidewall spacer structure contains nitrogen. Subsequent to its formation the sidewall spacer structure is annealed to harden the sidewall spacer str...	11/25/2008
7439124	Method of manufacturing a semiconductor device and semiconductor device Method of manufacturing a semiconductor device includes: forming a substrate protection film to cover an n-type FET forming region having a first gate electrode and a p-type FET forming region having a second gate electrode; opening the p-type FET forming region by ...	10/21/2008
7439123	Low resistance contact semiconductor device structure A method for making a semiconductor device structure includes producing a substrate having formed thereon a gate with spacers, respective source and drain regions adjacent to the gate and an; disposing a first metallic layer on the gate with spacers, and the source ...	10/21/2008
7432144	Method for forming a transistor for reducing a channel length A method of forming a transistor including: forming a gate oxide layer pattern and gate polysilicon layer pattern on a silicon substrate; forming a low energy ion implantation region aligned with both sidewalls of the gate polysilicon layer pattern; forming an amorp...	10/07/2008
7432570	Semiconductor device and manufacturing method thereof A semiconductor device includes a substrate, a p-channel MIS transistor formed on an n-type well on the substrate, having a first gate dielectric and a first gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111...	10/07/2008
7413946	Formation of standard voltage threshold and low voltage threshold MOSFET devices Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within...	08/19/2008
7410859	Stressed MOS device and method for its fabrication A stressed MOS device and a method for its fabrication are provided. The MOS device comprises a substrate having a surface, the substrate comprising a monocrystalline semiconductor material having a first lattice constant. A channel region is formed of the monocryst...	08/12/2008
7402485	Method of forming a semiconductor device A sidewall spacer structure is formed adjacent to a gate structure whereby a material forming an outer surface of the sidewall spacer structure contains nitrogen. Subsequent to its formation the sidewall spacer structure is annealed to harden the sidewall spacer str...	07/22/2008
7402484	Methods for forming a field effect transistor Methods for forming a field effect transistor are disclosed. An illustrated method comprises: forming a gate electrode on a substrate; and forming a nitride layer on at least a part of the gate electrode and the substrate. ...	07/22/2008
7390719	Method of manufacturing a semiconductor device having a dual gate structure A semiconductor device having a dual gate is formed on a substrate having a dielectric layer. A first metallic conductive layer is formed on the dielectric layer to a first thickness, and annealed to have a reduced etching rate. A second metallic conductive layer is...	06/24/2008
7390711	MOS transistor and manufacturing method thereof A MOS transistor including a gate insulation layer and a gate electrode layer on a channel region of a semiconductor substrate. A gate spacer layer is formed on a sidewall of the electrode layer and the insulation layer. The transistor includes a deep extended sourc...	06/24/2008
7384839	SRAM cell with asymmetrical transistors for reduced leakage A method of fabricating an SRAM cell with reduced leakage is disclosed. The method comprises fabricating asymmetrical transistors in the SRAM cell. The transistors are asymmetrical in a manner that reduces the drain leakage current of the transistors. The fabricatio...	06/10/2008
7378305	Semiconductor integrated circuit and fabrication process thereof A semiconductor integrated circuit device includes an n-channel MOS transistor formed on a first device region of a silicon substrate and a p-channel MOS transistor formed on a second device region of the silicon substrate, wherein the n-channel MOS transistor inclu...	05/27/2008
7378308	CMOS devices with improved gap-filling A semiconductor structure includes a substrate, and a first MOS device on the first region of the substrate wherein the first MOS device includes a first spacer liner. The semiconductor structure further includes a second MOS device on the second region wherein the ...	05/27/2008
7371647	Methods of forming transistors The invention encompasses a method of forming a structure over a semiconductor substrate. A silicon dioxide containing layer is formed across at least some of the substrate. Nitrogen is formed within the silicon dioxide containing layer. Substantially all of the nit...	05/13/2008
7371691	Silicon recess improvement through improved post implant resist removal and cleans The present invention provides a process of manufacturing a semiconductor device 200 while reducing silicon loss. In one aspect, the process includes removing a photoresist layer 270 from a semiconductor substrate 235 adjacent a gate 240 ...	05/13/2008
7371646	Manufacture of insulated gate type field effect transistor After a field insulating film having an element opening is formed on the surface of a p-type well, a gate insulating film is formed on a semiconductor surface in the element opening. A gate electrode layer of polysilicon or the like is formed on the insulating film....	05/13/2008
7368792	MOS transistor with elevated source/drain structure In a metal-oxide semiconductor (MOS) transistor with an elevated source/drain structure and in a method of fabricating the MOS transistor with the elevated source/drain structure using a selective epitaxy growth (SEG) process, a source/drain extension junction is fo...	05/06/2008
7361539	Dual stress liner A semiconductor device structure is provided which includes a first field effect transistor (“FET”) having a first channel region, a first source region, a first drain region and a first gate conductor overlying the first channel region. A second FET is included...	04/22/2008
7358168	Ion implantation method for forming a shallow junction A shallow junction that previously would require the use of a low-energy ion implanter can be directly formed by high-energy or middle-energy ion implanters such that the manufacturer need not purchase a new low-energy ion implanter. In one embodiment, an ion-implan...	04/15/2008
7358134	Split gate flash memory cell and manufacturing method thereof A split gate flash memory cell includes a substrate having a device isolation structure; a selective gate structure disposed on the substrate; an interlayer dielectric layer having an opening disposed on the substrate, wherein the opening exposes a portion of the se...	04/15/2008
7354838	Technique for forming a contact insulation layer with enhanced stress transfer efficiency By removing an outer spacer, used for the formation of highly complex lateral dopant profiles, prior to the formation of metal silicide, a high degree of process compatibility with conventional processes is obtained, while at the same time a contact liner layer may ...	04/08/2008
7355256	MOS Devices with different gate lengths and different gate polysilicon grain sizes A semiconductor device 1 according to the present invention includes a semiconductor substrate 5, a first transistor 10 which is formed on the semiconductor substrate 5 and includes a first gate electrode portion 16 constituted by ...	04/08/2008
7355246	Memory cell without halo implant Some embodiments provide a memory cell comprising a body region doped with charge carriers of a first type, a source region disposed in the body region and doped with charge carriers of a second type, and a drain region disposed in the body region and doped with cha...	04/08/2008
7351627	Method of manufacturing semiconductor device using gate-through ion implantation Disclosed herein is a method of manufacturing a semiconductor device via gate-through ion implantation, comprising forming a gate stack on a semiconductor substrate and performing ion implantation for control of the threshold voltage and junction ion implantation fo...	04/01/2008
7348249	Method for manufacturing semiconductor device A method for manufacturing a semiconductor device reduces or prevents copper contamination. The method includes forming a gate electrode on a substrate; forming a first oxide layer on a front surface of the substrate including the gate electrode; depositing a nitrid...	03/25/2008
7341901	Semiconductor processing methods of forming integrated circuitry Semiconductor processing methods of forming integrated circuitry are described. In one embodiment, memory circuitry and peripheral circuitry are formed over a substrate. The peripheral circuitry comprises first and second type MOS transistors. Second type halo impla...	03/11/2008
7341906	Method of manufacturing sidewall spacers on a memory device, and device comprising same The present invention is generally directed to a method of manufacturing sidewall spacers on a memory device, and a memory device comprising such sidewall spacers. In one illustrative embodiment, the method includes forming sidewall spacers on a memory device compri...	03/11/2008
7335540	Low temperature polysilicon thin film transistor and method of manufacturing the same A low temperature polysilicon thin film transistor and method of manufacturing the same is provided. The low temperature polysilicon thin film transistor comprises a channel region. Among others, one feature of the method according to the present invention is the pe...	02/26/2008
7335544	Method of making MOSFET device with localized stressor A metal-oxide-semiconductor field-effect transistors (MOSFET) having localized stressors is provided. In accordance with embodiments of the present invention, a transistor comprises a high-stress film over the source/drain regions, but not over the gate electrode. T...	02/26/2008
7335959	Device with stepped source/drain region profile Embodiments of the invention provide a transistor with stepped source and drain regions. The stepped regions may provide significant strain in a channel region while minimizing current leakage. The stepped regions may be formed by forming two recesses in a substrate...	02/26/2008
7332755	Transistor structure of memory device and method for fabricating the same A memory device includes an active area protruding from a semiconductor substrate. A recess is formed in the active area. A field oxide layer is formed on the semiconductor substrate. A gate electrode extends across the active area while being overlapped with the re...	02/19/2008
7329571	Technique for providing multiple stress sources in NMOS and PMOS transistors By combining a plurality of stress inducing mechanisms in each of different types of transistors, a significant performance gain may be obtained, thereby providing enhanced flexibility in adjusting product specific characteristics. For this purpose, sidewall spacers...	02/12/2008
7326988	Semiconductor device and method for fabricating the same A metal film formed of a first metal having relatively high oxygen absorption properties on a silicon region, and then depositing a high dielectric constant film formed of an oxide of a second metal having relatively low oxygen absorption properties on the metal fil...	02/05/2008

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Class 438/231 - Plural doping steps