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Actor Marlon Brando has four patents, all named "Drumhead tensioning device and method."
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| Number | Title | Issue Date |
| 8114730 | Shared contact structure, semiconductor device and method of fabricating the semiconductor device A shared contact structure, semiconductor device and method of fabricating the semiconductor device, in which the shared contact structure may include a gate electrode disposed on an active region of a substrate and including facing first and second sidewalls. The f... | 02/14/2012 |
| 8058123 | Integrated circuit and method of fabrication thereof A method of forming an integrated circuit structure comprising the steps of forming a first and second device region on a surface of a wafer, forming a spacer of a first width on a sidewall of a first gate stack in the first device region, forming a spacer of a seco... | 11/15/2011 |
| 8030154 | Method for forming a protection layer over metal semiconductor contact and structure formed thereon In one embodiment, a method of forming a semiconductor device is provided that includes providing a gate structure on a semiconductor substrate. Sidewall spacers may be formed adjacent to the gate structure. A metal semiconductor alloy may be formed on the upper sur... | 10/04/2011 |
| 8026136 | Methods of forming low hydrogen concentration charge-trapping layer structures for non-volatile memory Memory cells comprising: a semiconductor substrate having at least two source/drain regions separated by a channel region; a charge-trapping structure disposed above the channel region; and a gate disposed above the charge-trapping structure; wherein the charge-trap... | 09/27/2011 |
| 8021944 | Method for fabricating semiconductor device A method for fabricating a semiconductor device is disclosed. The method includes: forming a photoresist film on a semiconductor substrate including a silicide forming region and non-silicide forming region; forming a photoresist pattern as a non-salicide pattern by... | 09/20/2011 |
| 7968401 | Reducing photoresist layer degradation in plasma immersion ion implantation A method of plasma immersion ion implantation of a workpiece having a photoresist mask on its top surface prevents photoresist failure from carbonization of the photoresist. The method includes performing successive ion implantation sub-steps, each of the ion implan... | 06/28/2011 |
| 7943462 | Transistor including a high-K metal gate electrode structure formed prior to drain/source regions on the basis of a sacrificial carbon spacer When forming sophisticated high-k metal gate electrode structures in an early manufacturing stage, the dielectric cap layer of the gate electrode structures may be efficiently removed on the basis of a carbon spacer element, which may thus preserve the integrity of ... | 05/17/2011 |
| 7935592 | Method of manufacturing semiconductor device having of spacer gate structure In a case of using a silicon nitride film as an offset spacer for forming an extension region of a transistor, an oxide protective surface is formed by oxygen plasma processing on the surface of the silicon nitride film. ... | 05/03/2011 |
| 7923321 | Method for gap filling in a gate last process A method is provided for fabricating a semiconductor device that includes providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the substrate, forming a silicon layer over the high-k dielectric layer, f... | 04/12/2011 |
| 7902021 | Method for separately optimizing spacer width for two or more transistor classes using a recess spacer integration A method for making a semiconductor device is disclosed. In accordance with the method, a semiconductor structure is provided which includes (a) a substrate (203), (b) first and second gate electrodes (219) disposed over the substrate, each of the firs... | 03/08/2011 |
| 7851299 | Subgroundrule space for improved metal high-k device The present invention provides a semiconducting device including a substrate including at least one semiconducting region and isolation regions; a gate structure atop the substrate having a gate dielectric layer positioned on the semiconducting region and a metal la... | 12/14/2010 |
| 7799630 | Method for manufacturing a CMOS device having dual metal gate A method for manufacturing a CMOS device having dual metal gate includes providing a substrate having at least two transistors of different conductive types and a dielectric layer covering the two transistors, planarizing the dielectric layer to expose gate conducti... | 09/21/2010 |
| 7781282 | Shared contact structure, semiconductor device and method of fabricating the semiconductor device A shared contact structure, semiconductor device and method of fabricating the semiconductor device, in which the shared contact structure may include a gate electrode disposed on an active region of a substrate and including facing first and second sidewalls. The f... | 08/24/2010 |
| 7732272 | Method of manufacturing semiconductor element A method of manufacturing a semiconductor device includes a process of forming a gate electrode having a metallic silicide layer on a semiconductor substrate, a process of decreasing boundaries of grains on the surface of the metallic silicide layer, at least a port... | 06/08/2010 |
| 7718485 | Interlayer dielectric under stress for an integrated circuit An integrated circuit that has logic and a static random access memory (SRAM) array has improved performance by treating the interlayer dielectric (ILD) differently for the SRAM array than for the logic. The N channel logic and SRAM transistors have ILDs with non-co... | 05/18/2010 |
| 7713810 | Method for fabricating a layer arrangement, layer arrangement and memory arrangement The disclosed embodiments relate to a method for the production of a layer arrangement, a layer arrangement and a memory arrangement. According to one aspect at least one respectively laterally defined first layer sequence is embodied on a first surface area of a su... | 05/11/2010 |
| 7642152 | Method of fabricating spacers and cleaning method of post-etching and semiconductor device A method of fabricating spacers is provided. The method includes providing a substrate with a device structure formed thereon. The device structure comprises a gate structure and a pair of source/drain regions. Then, a spacer material layer is formed over the substr... | 01/05/2010 |
| 7642153 | Methods for forming gate electrodes for integrated circuits A method of forming an integrated circuit can include the steps of providing a substrate having a semiconducting surface and forming a plurality of semiconducting multilayer features on the substrate surface, the features comprising a base layer and a compositionall... | 01/05/2010 |
| 7629215 | Semiconductor device and method of manufacturing the same A semiconductor device includes first gate structures, second gate structures, a first capping layer pattern, a second capping layer pattern, first spacers, second spacers, third spacers, and a substrate having first impurity regions and second impurity regions. The... | 12/08/2009 |
| 7560331 | Method for forming a silicided gate A gate is silicided through its sides while limiting silicidation through the top of the gate. A blocking layer may be formed over the gate layer, and the sidewalls of the gate layer are exposed. A layer of metal is formed on the sidewalls of the gate and thermally ... | 07/14/2009 |
| 7541239 | Selective spacer formation on transistors of different classes on the same device A method of selectively forming a spacer on a first class of transistors and devices formed by such methods. The method can include depositing a conformal first deposition layer on a substrate with different classes of transistors situated thereon, depositing a bloc... | 06/02/2009 |
| 7521314 | Method for selective removal of a layer A method for forming a semiconductor device includes forming a liner over a semiconductor material including a control electrode. The method further includes forming a first spacer adjacent to the control electrode, wherein the first spacer has a first width. The me... | 04/21/2009 |
| 7485524 | MOSFETs comprising source/drain regions with slanted upper surfaces, and method for fabricating the same The present invention relates to improved metal-oxide-semiconductor field effect transistor (MOSFET) devices comprising source and drain (S/D) regions having slanted upper surfaces with respect to a substrate surface. Such S/D regions may comprise semiconductor stru... | 02/03/2009 |
| 7432144 | Method for forming a transistor for reducing a channel length A method of forming a transistor including: forming a gate oxide layer pattern and gate polysilicon layer pattern on a silicon substrate; forming a low energy ion implantation region aligned with both sidewalls of the gate polysilicon layer pattern; forming an amorp... | 10/07/2008 |
| 7416940 | Methods for fabricating flash memory devices Methods for fabricating a flash memory device are provided. A method comprises forming a plurality of gate stacks overlying a substrate. Each gate stack comprises a charge trapping layer and a control gate. The control gate is a first distance from the substrate. Ad... | 08/26/2008 |
| 7416927 | Method for producing an SOI field effect transistor Method for producing a first SOI field effect transistor with predetermined transistor properties by forming a laterally delimited layer sequence with a gate-insulating layer and a gate region on an undoped substrate, forming a spacer layer having a predetermined th... | 08/26/2008 |
| 7396716 | Method to obtain fully silicided poly gate The present invention provides a method of fabricating a microelectronics device. In one aspect, the method comprises forming a capping layer 610 over gate structures 230 located over a microelectronics substrate 210 wherein the gate structures ... | 07/08/2008 |
| 7384838 | Semiconductor FinFET structures with encapsulated gate electrodes and methods for forming such semiconductor FinFET structures Semiconductor structures in which the gate electrode of a FinFET is masked from the process introducing dopant into the fin body of the FinFET to form source/drain regions and methods of fabricating such semiconductor structures. The gate doping, and hence the work ... | 06/10/2008 |
| 7381623 | Pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performance The embodiments of the invention provide a method, etc. for a pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performance. More specifically, one method begins by forming a first gate and a second ga... | 06/03/2008 |
| 7371648 | Method for manufacturing a transistor device having an improved breakdown voltage and a method for manufacturing an integrated circuit using the same The present invention provides a method for manufacturing a transistor device, and a method for manufacturing an integrated circuit including the same. The method for manufacturing the transistor device, among other elements, includes forming a gate structure over a... | 05/13/2008 |
| 7368792 | MOS transistor with elevated source/drain structure In a metal-oxide semiconductor (MOS) transistor with an elevated source/drain structure and in a method of fabricating the MOS transistor with the elevated source/drain structure using a selective epitaxy growth (SEG) process, a source/drain extension junction is fo... | 05/06/2008 |
| 7368372 | Methods of fabricating multiple sets of field effect transistors The invention includes methods of fabricating multiple sets of field effect transistors. In one implementation, an etch stop layer is formed over an insulative capping layer which is formed over a conductive gate layer formed over a substrate. The etch stop layer, t... | 05/06/2008 |
| 7364963 | Method for fabricating semiconductor device A method for fabricating a semiconductor device is provided. The method includes: implanting impurities onto a substrate by performing an ion implantation process; recessing portions of the substrate to form a plurality of trenches; performing a first thermal proces... | 04/29/2008 |
| 7364995 | Method of forming reduced short channel field effect transistor A method for manufacturing a semiconductor device capable of reducing a short channel effect, whereby the semiconductor device includes a pair of impurity regions for a source and a drain formed on a semiconductor substrate, a gate having a gate electrode used to co... | 04/29/2008 |
| 7344937 | Methods and apparatus with silicide on conductive structures Exemplary embodiments of the invention provide pixel circuits having transistors with silicide on top of their gate stacks. In the exemplary embodiments, silicide forming material does not contaminate other components such as the photoconversion devices of an imager... | 03/18/2008 |
| 7342276 | Method and apparatus utilizing monocrystalline insulator A semiconductor device, including: a semiconductor material; a conductive element; and a substantially monocrystalline insulator disposed between the semiconductor material and the conductive eleme... | 03/11/2008 |
| 7341903 | Method of forming a field effect transistor having a stressed channel region A semiconductor structure comprises a transistor element formed in a substrate. A stressed layer is formed over the transistor element. The stressed layer has a predetermined compressive intrinsic stress having an absolute value of about 1 GPa or more. Due to this h... | 03/11/2008 |
| 7341906 | Method of manufacturing sidewall spacers on a memory device, and device comprising same The present invention is generally directed to a method of manufacturing sidewall spacers on a memory device, and a memory device comprising such sidewall spacers. In one illustrative embodiment, the method includes forming sidewall spacers on a memory device compri... | 03/11/2008 |
| 7335589 | Method of forming contact via through multiple layers of dielectric material In a manufacture of a semiconductor device, spacers are formed on sidewalls of structures including conductive patterns and insulation patterns. The insulation patterns are at least four times thinner than the conductive patterns. After gaps between the structures a... | 02/26/2008 |
| 7326613 | Methods of manufacturing semiconductor devices having elongated contact plugs A method of manufacturing a semiconductor device includes forming conductive structures on a substrate. Each of the conductive structures has a line shape that extends along a first direction parallel to the substrate. Insulating spacers are formed on upper sidewall... | 02/05/2008 |
