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| Number | Title | Issue Date |
| 8124472 | Manufacturing method of a semiconductor device A semiconductor device includes a first pMISFET region having an Si channel, a second pMISFET region having an Si channel and an nMISFET region having an Si channel. First SiGe layers which apply first compression strain to the Si channel are embedded and formed in ... | 02/28/2012 |
| 8114729 | Differential poly doping and circuits therefrom A method of fabricating a CMOS integrated circuit and integrated circuits therefrom includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric layer on the semiconductor surface and a polysilicon including layer on the gate... | 02/14/2012 |
| 8076194 | Method of fabricating metal oxide semiconductor transistor A method of fabricating a MOS transistor is disclosed. The method includes the steps of: providing a semiconductor substrate; forming at least a gate on the semiconductor substrate; forming a protective layer on the semiconductor substrate, and the protective layer ... | 12/13/2011 |
| 7985643 | Semiconductor transistors with contact holes close to gates A semiconductor structure. The structure includes (a) a semiconductor layer including a channel region disposed between first and second S/D regions; (b) a gate dielectric region on the channel region; (c) a gate region on the gate dielectric region and electrically... | 07/26/2011 |
| 7981740 | Enhanced cap layer integrity in a high-K metal gate stack by using a hard mask for offset spacer patterning When forming transistor elements on the basis of sophisticated high-k metal gate structures, the efficiency of a replacement gate approach may be enhanced by more efficiently adjusting the gate height of transistors of different conductivity type when the dielectric... | 07/19/2011 |
| 7790545 | Semiconductor device having a polysilicon electrode including amorphizing, recrystallising, and removing part of the polysilicon electrode A method of manufacturing a semiconductor device such as a MOS transistor. The device comprises a polysilicon gate (10) and doped regions (22,24) formed in a semiconductor substrate (12), separated by a channel region (26). The exposed su... | 09/07/2010 |
| 7785957 | Post metal gate VT adjust etch clean A method for fabricating a CMOS integrated circuit (IC) includes providing a substrate having a semiconductor surface, wherein the semiconductor surface has PMOS regions for PMOS devices and NMOS regions for NMOS devices. A gate dielectric layer is formed on the sem... | 08/31/2010 |
| 7781281 | Method of fabricating self-aligned contact pad using chemical mechanical polishing process A method of fabricating a self-aligned contact pad (SAC) includes forming stacks of a conductive line and a capping layer on a semiconductor substrate, spacers covering sidewalls of the stacks, and an insulation layer filling gaps between the stacks and exposing the... | 08/24/2010 |
| 7691701 | Method of forming gate stack and structure thereof Embodiments of the present invention provide a method of forming gate stacks for field-effect-transistors. The method includes forming a metal-containing layer directly on a first titanium-nitride (TiN) layer, the first TiN layer covering areas of a semiconductor su... | 04/06/2010 |
| 7608501 | Technique for creating different mechanical strain by forming a contact etch stop layer stack having differently modified intrinsic stress By partially removing an etch stop layer prior to the formation of a first contact etch stop layer, a superior stress transfer mechanism may be provided in an integration scheme for generating strain by means of contact etch stop layers. Thus, a semiconductor device... | 10/27/2009 |
| 7592215 | Semiconductor device having self-aligned contact hole and method of fabricating the same According to embodiments of the invention, word line patterns are placed on a semiconductor substrate in a cell array region and at least one gate pattern is placed on the semiconductor substrate in a peripheral circuit region. Side walls of the word line patterns a... | 09/22/2009 |
| 7537990 | Method of manufacturing semiconductor devices A method of manufacturing semiconductor devices includes: preparing a semiconductor substrate over which a laminated structure including an insulating layer is formed; forming over the insulating layer a resist mask including a first opening and a second opening whi... | 05/26/2009 |
| 7521313 | Thin film device active matrix by pattern reversal process This invention provides a method of fabricating an active matrix of thin film devices through a pattern reversal self aligned imprint lithography (SAIL) process. The method includes providing a substrate and depositing at least one layer of material upon the substra... | 04/21/2009 |
| 7432144 | Method for forming a transistor for reducing a channel length A method of forming a transistor including: forming a gate oxide layer pattern and gate polysilicon layer pattern on a silicon substrate; forming a low energy ion implantation region aligned with both sidewalls of the gate polysilicon layer pattern; forming an amorp... | 10/07/2008 |
| 7399669 | Semiconductor devices and methods for fabricating the same including forming an amorphous region in an interface between a device isolation layer and a source/drain diffusion layer Semiconductor devices and methods for fabricating the same are disclosed in which an amorphous layer is formed in an interface between a device isolation layer and a source or drain region to stably thin a silicide layer formed in the interface. A leakage current of... | 07/15/2008 |
| 7381610 | Semiconductor transistors with contact holes close to gates A structure and a method for forming the same. The structure includes (a) a semiconductor layer including a channel region disposed between first and second S/D regions; (b) a gate dielectric region on the channel region; (c) a gate region on the gate dielectric reg... | 06/03/2008 |
| 7382054 | Method for forming self-aligned contacts and local interconnects simultaneously The present invention relates generally to semiconductors, and more specifically to semiconductor memory device structures and an improved fabrication process for making the same. The improved fabrication process allows the self-aligned contacts and local interconne... | 06/03/2008 |
| 7371629 | N/PMOS saturation current, HCE, and Vt stability by contact etch stop film modifications A method is provided for improving Idsat in NMOS and PMOS transistors. A silicon nitride etch stop layer is deposited by a PECVD technique on STI and silicide regions and on sidewall spacers during a MOSFET manufacturing scheme. A dielectric layer is formed on the n... | 05/13/2008 |
| 7364963 | Method for fabricating semiconductor device A method for fabricating a semiconductor device is provided. The method includes: implanting impurities onto a substrate by performing an ion implantation process; recessing portions of the substrate to form a plurality of trenches; performing a first thermal proces... | 04/29/2008 |
| 7364989 | Strain control of epitaxial oxide films using virtual substrates A method of controlling strain in a single-crystal, epitaxial oxide film, includes preparing a silicon substrate; forming a silicon alloy layer taken from the group of silicon alloy layer consisting of Si1-xGex and Si1-yCy | 04/29/2008 |
| 7326606 | Semiconductor processing methods In one aspect, the invention provides a method of forming a contact opening to a conductive line. In one preferred implementation, a contact opening is formed to a conductive line which overlies a substrate isolation area with an etch which also outwardly exposes su... | 02/05/2008 |
| 7323381 | Semiconductor device and manufacturing method thereof A structure of a MIS transistor for realizing a CMOS circuit capable of simultaneously achieving the high ON current and the low power consumption is provided. Each of the gate insulators of an n channel MIS transistor and a p channel MIS transistor is composed of a... | 01/29/2008 |
| 7312125 | Fully depleted strained semiconductor on insulator transistor and method of making the same An integrated circuit includes multiple layers. A semiconductor-on-insulator (SOI) wafer can be used to house transistors. Two substrates or wafers can be bonded to form the multiple layers. A strained semiconductor layer can be between a silicon germanium layer and... | 12/25/2007 |
| 7297588 | Electronic device comprising a gate electrode including a metal-containing layer having one or more impurities and a process for forming the same One or more impurities may be incorporated within a metal-containing layer of a metal-containing gate electrode to modify the work function of the metal-containing gate electrode of a transistor can affect the threshold voltage of the transistor. In one embodiment, ... | 11/20/2007 |
| 7229871 | Integrated circuit containing polysilicon gate transistors and fully silicidized metal gate transistors A method for manufacturing an integrated circuit 10 having transistors 20, 30 of two threshold voltages where protected transistor stacks 270 have a gate protection layer 220 that are formed with the use of a single additional mask step. ... | 06/12/2007 |
| 7223650 | Self-aligned gate isolation Embodiments of the invention include a circuit with a transistor having a self-aligned gate. Insulating isolation structures may be formed, self-aligned to diffusions. The gate may then be formed self-aligned to the insulating isolation structures. ... | 05/29/2007 |
| 7220632 | Method of forming a semiconductor device and an optical device and structure thereof An integration process where a first semiconductor protective layer and a second semiconductor protective layer are formed to protect the first and second semiconductor materials, respectfully, during processing to form an optical device, such as a photodetector, an... | 05/22/2007 |
| 7190823 | Overlay vernier pattern for measuring multi-layer overlay alignment accuracy and method for measuring the same An overlay vernier pattern for measuring multi-layer overlay alignment accuracy and a method for measuring the same is provided. A distance between a first alignment mark in a first material layer and a second alignment mark in an underlying second material layer is... | 03/13/2007 |
| 7187038 | Semiconductor device with MOS transistors with an etch-stop layer having an improved residual stress level and method for fabricating such a semiconductor device A semiconductor device includes a substrate, MOS transistors in the substrate, and a dielectric layer on the MOS transistors. Contact holes are formed through the dielectric layer to provide electrical connection to the MOS transistors. An etch-stop layer is between... | 03/06/2007 |
| 7148097 | Integrated circuit containing polysilicon gate transistors and fully silicidized metal gate transistors A method for manufacturing an integrated circuit 10 having transistors 20, 30 of two threshold voltages where protected transistor stacks 270 have a gate protection layer 220 that are formed with the use of a single additional mask step. ... | 12/12/2006 |
| 7144767 | NFETs using gate induced stress modulation A method for manufacturing an integrated circuit comprising a plurality of semiconductor devices including an n-type field effect transistor and a p-type field effect transistor by covering the p-type field effect transistor with a mask, and oxidizing a portion of a... | 12/05/2006 |
| 7119016 | Deposition of carbon and nitrogen doped poly silicon films, and retarded boron diffusion and improved poly depletion A compound that includes at least Si, N and C in any combination, such as compounds of formula (R—NH)4-nSiXn wherein R is an alkyl group (which may be the same or different), n is 1, 2 or 3, and X is H or halogen (such as, e.g., bis-tertiary ... | 10/10/2006 |
| 7115491 | Method for forming self-aligned contact in semiconductor device A method for forming a self-aligned contact on a semiconductor substrate provided with a plurality of field-effect transistors. The method comprises the steps of: forming a thin nitride insulating layer on a gate structure and a diffusion region of the transistor; f... | 10/03/2006 |
| 7098098 | Methods for transistors formation using selective gate implantation Methods are disclosed for semiconductor device fabrication in which dopants are selectively implanted into transistor gate structures to counteract or compensate for dopant depletion during subsequent fabrication processing. A patterned implant mask is formed over a... | 08/29/2006 |
| 7098099 | Semiconductor device having optimized shallow junction geometries and method for fabrication thereof The present invention provides, in one embodiment, a method of fabricating a semiconductor device (100). In one embodiment, the method includes growing an oxide layer 120 from a substrate 104, 106 over a first dopant region 122 and a seco... | 08/29/2006 |
| 7087475 | Semiconductor device having a plurality of gate electrodes and manufacturing method thereof A semiconductor device includes first and second gate electrode, first and second gate insulating film, semiconductor layer, source and drain regions, and source and drain electrodes. The first gate electrode is formed in the insulating film. The first gate insulati... | 08/08/2006 |
| 7078339 | Method of forming metal line layer in semiconductor device The present invention is provided to form a metal line layer in a semiconductor device, wherein at least one conductive layer of a plurality of conductive layers is etched, a side wall oxide film is formed on side walls of some conductive layers of the etched conduc... | 07/18/2006 |
| 7077904 | Method for atomic layer deposition (ALD) of silicon oxide film The present invention relates to a method for forming silicon oxide films on substrates using an atomic layer deposition process. Specifically, the silicon oxide films are formed at low temperature and high deposition rate via the atomic layer deposition process usi... | 07/18/2006 |
| 7045408 | Integrated circuit with improved channel stress properties and a method for making it An integrated circuit is described that comprises a PMOS transistor and an NMOS transistor that are formed on a semiconductor substrate. A silicate glass layer is formed on only the PMOS transistor or the NMOS transistor; and an etch stop layer is formed on the sili... | 05/16/2006 |
| 7045412 | Field-effect type semiconductor device for power amplifier In a semiconductor multi-layer structure in which a first SiGe layer having a first conductivity-type and high impurity concentration, a second SiGe layer having the first conductivity-type and a low impurity concentration and a Si layer having a low impurity concen... | 05/16/2006 |
