Did You Know...
...Chester Carlson was a patent agent who tired of having to make multiple copies of patent applications using the only duplication method available at the time: carbon paper. In 1959 he came up with a new copying system and took it to IBM for evaluation. The "experts" at IBM determined potential sales to be only 5,000 units because people wouldn't want to use a bulky machine when they had carbon paper. Carlson's invention was the xerography process, the company founded on the system is Xerox.
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| Number | Title | Issue Date |
| 7902020 | Semiconductor device and method of manufacturing the same A semiconductor device includes a first conductivity-type deep well formed in a substrate, a plurality of device isolation layers formed in the substrate in which the first conductivity-type deep well is formed, a second conductivity-type well formed on a portion of... | 03/08/2011 |
| 7691700 | Multi-stage implant to improve device characteristics One aspect of the inventors' concept relates to a method of forming a semiconductor device. In this method, a gate structure is formed over a semiconductor body. A source/drain mask is patterned over the semiconductor body implanted source and drain regions are form... | 04/06/2010 |
| 7682895 | Semiconductor device and method of manufacturing the same A method of manufacturing a semiconductor device includes: (A) a wafer process; and (B) a bias application process after the wafer process. The wafer process includes: (a) forming a n-type well in a p-type semiconductor substrate; (b) forming a p-type well in the n-... | 03/23/2010 |
| 7482220 | Semiconductor device having deep trench charge compensation regions and method In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a charge compensating trench formed in proximity to active portions of the device. The charge compensating trench includes a trench filled with... | 01/27/2009 |
| 7410855 | Semiconductor device A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected f... | 08/12/2008 |
| 7364959 | Method for manufacturing a MOS transistor A method for manufacturing a MOS transistor integrated into a chip of semi-conductive material comprising a first and a second active region which extend from the inside of the chip to a surface of the chip. The method comprises the steps of: a) forming a layer of i... | 04/29/2008 |
| 7364997 | Methods of forming integrated circuitry and methods of forming local interconnects In one implementation, field oxide is grown within bulk semiconductive material in a first circuitry area and not over immediately adjacent bulk semiconductive material in a second circuitry area. The field oxide is etched from the first circuitry area. After the et... | 04/29/2008 |
| 7358596 | Device isolation for semiconductor devices Exemplary embodiments of the present invention disclose a semiconductor assembly having at least one isolation structure formed. The semiconductor assembly comprises: a first trench in a semiconductive substrate; a second trench extending the overall trench depth in... | 04/15/2008 |
| 7351627 | Method of manufacturing semiconductor device using gate-through ion implantation Disclosed herein is a method of manufacturing a semiconductor device via gate-through ion implantation, comprising forming a gate stack on a semiconductor substrate and performing ion implantation for control of the threshold voltage and junction ion implantation fo... | 04/01/2008 |
| 7336530 | CMOS pixel with dual gate PMOS A pixel circuit with a dual gate PMOS is formed by forming two P+ regions in an N− well. The N− well is in a P− type substrate. The two P+ regions form the source and drain of a PMOS transistor. The PMOS t... | 02/26/2008 |
| 7335543 | MOS device for high voltage operation and method of manufacture A high voltage semiconductor device. The high voltage device has a substrate (e.g., silicon wafer) having a surface region. The substrate has a well region within the substrate and a double diffused drain region within the well region. A gate dielectric layer is ove... | 02/26/2008 |
| 7329618 | Ion implanting methods An ion implanting method includes forming a pair of spaced and adjacent features projecting outwardly from a substrate. At least outermost portions of the pair of spaced features are laterally pulled away from one another with a patterned photoresist layer received ... | 02/12/2008 |
| 7314621 | Cytidine deaminase Antibodies that specifically bind to AID (Activation-Induced cytidine Deaminase) proteins, compositions comprising said antibodies, and cells producing said antibodies, are described. The AID proteins are structurally related to APOBEC-1,l an RNA editing enzyme, and... | 01/01/2008 |
| 7309636 | High-voltage metal-oxide-semiconductor device and method of manufacturing the same The present invention pertains to a high-voltage MOS device. The high-voltage MOS device includes a substrate, a first well, a first field oxide layer enclosing a drain region, a second field oxide enclosing a source region, and a third field oxide layer encompassin... | 12/18/2007 |
| 7301221 | Controlling diffusion in doped semiconductor regions A method and device for reducing a dopant diffusion rate in a doped semiconductor region is provided. The methods and devices include selecting a plurality of impurity elements, including at least one dopant element. Selection of a plurality of impurity elements inc... | 11/27/2007 |
| 7294551 | Semiconductor device and method for manufacturing the same A semiconductor device has a gate electrode formed on a P type semiconductor substrate via gate oxide films. A first low concentration (LN type) drain region is made adjacent to one end of the gate electrode. A second low concentration (SLN type) drain region is for... | 11/13/2007 |
| 7279378 | Method of fabricating isolated semiconductor devices in epi-less substrate An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does... | 10/09/2007 |
| 7265405 | Method for fabricating contacts for integrated circuits, and semiconductor component having such contacts One (or more) contacts are produced on one or more active areas of a semiconductor wafer, it being possible for one or more isolated control lines to be arranged on the active areas with which contact is to be made. The control lines may, for example, be gate lines.... | 09/04/2007 |
| 7259071 | Semiconductor device with dual gate oxides A method for making a semiconductor device having a first active region and a second active region includes providing first and second isolation structures defining the first active region on a substrate. The first active region uses a first operational voltage, and... | 08/21/2007 |
| 7251403 | Light scattering structures formed in silicon waveguides In a standard CMOS process, a layer of metallic salicide can be deposited on those selected portions of an integrated circuit, where it is desired to have metallic contacts for electronic components, such as transistors. The deposition of a salicide into optical ele... | 07/31/2007 |
| 7247534 | Silicon device on Si:C-OI and SGOI and method of manufacture A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a second material on the substrate. The first material and the second mat... | 07/24/2007 |
| 7235460 | Method of forming active and isolation areas with split active patterning A process for forming isolation and active regions, wherein the patterning of an oxidation-barrier active stack is performed separately in the PMOS and NMOS regions. After the active stack is in place, two masking steps are used: one exposes the isolation areas on t... | 06/26/2007 |
| 7221591 | Fabricating bi-directional nonvolatile memory cells A memory transistor having a pair of separate floating gates overlying end regions of a channel and a control gate that overlies the floating gates and a central region of the channel effectively operates as a pair of floating gate transistors with an intervening se... | 05/22/2007 |
| 7221009 | Semiconductor device A dose of arsenic for an extension region in an NMOS transistor is in a range from 5×1014 to 2×1015 ions/cm2 and preferably in a range from 1.1×1015 to 1.5×1015 ions/cm2. Also, in addition to arse... | 05/22/2007 |
| 7208805 | Structures comprising a layer free of nitrogen between silicon nitride and photoresist The invention includes a semiconductor processing method. A first material comprising silicon and nitrogen is formed. A second material is formed over the first material, and the second material comprises silicon and less nitrogen, by atom percent, than the first ma... | 04/24/2007 |
| 7163856 | Method of fabricating a lateral double-diffused mosfet (LDMOS) transistor and a conventional CMOS transistor A method of fabricating an LDMOS transistor and a conventional CMOS transistor together on a substrate. A P-body is implanted into a source region of the LDMOS transistor. A gate oxide for the conventional CMOS transistor is formed after implanting the P-body into t... | 01/16/2007 |
| 7145187 | Substrate independent multiple input bi-directional ESD protection structure In a multiple input ESD protection structure, the inputs are isolated from the substrate by highly doped regions of opposite polarity to the input regions. Dual polarity is achieved by providing a symmetrical structure with n+ and p+ regions forming each dual polari... | 12/05/2006 |
| 7132323 | CMOS well structure and method of forming the same A method for forming a CMOS well structure including forming a plurality of first conductivity type wells over a substrate, each of the plurality of first conductivity type wells formed in a respective opening in a first mask. A cap is formed over each of the first ... | 11/07/2006 |
| 7098122 | Method of fabricating a vertically integrated memory cell A unique cell structure for use in flash memory cell and a method of fabricating the memory cell. More particularly, a vertically integrated transistor having a pair of floating gates is fabricated within a trench in a substrate. The floating gates are fabricated us... | 08/29/2006 |
| 7060598 | Method for implanting ions into semiconductor substrate An ion implantation method for implanting ions into a side wall of a protruded semiconductor layer from a semiconductor substrate, the method includes applying an electric field to accelerate the ions in one direction and applying a magnetic field parallel to a plan... | 06/13/2006 |
| 7049665 | Method of manufacturing a dual gate semiconductor device with a poly-metal electrode In order to realize a dual gate CMOS semiconductor device with little leakage of boron that makes it possible to divisionally doping a p-type impurity and an n-type impurity into a polycrystalline silicon layer with one mask, a gate electrode has a high melting poin... | 05/23/2006 |
| 7049669 | LDMOS transistor A semiconductor device comprises an active region of a first conductivity type including a transistor structure, and a ring shaped region of the first conductivity type extending from a surface of the active region into the active region and substantially surroundin... | 05/23/2006 |
| 7049206 | Device isolation for semiconductor devices Exemplary embodiments of the present invention disclose a semiconductor assembly having at least one isolation structure formed. The semiconductor assembly comprises: a first trench in a semiconductive substrate; a second trench extending the overall trench depth in... | 05/23/2006 |
| 7045414 | Method of fabricating high voltage transistor A high voltage MOS transistor has a thermally-driven-in first doped region and a second doped region that form a double diffused drain structure. Boundaries of the first doped region are graded. A gate-side boundary of the first doped region extends laterally below ... | 05/16/2006 |
| 7018899 | Methods of fabricating lateral double-diffused metal oxide semiconductor devices Methods for fabricating LDMOS transistors are disclosed. A disclosed method includes: forming a device isolation structure in a semiconductor substrate through an STI process; forming a photoresist pattern exposing the device isolation structure; forming double diff... | 03/28/2006 |
| 7005340 | Method for manufacturing semiconductor device A method is provided for manufacturing a semiconductor device that can reduce the number of steps in manufacturing a triple-well that includes multiple ion implantation steps and heat treatment steps. The method comprises the steps of: (a) forming a first mask layer... | 02/28/2006 |
| 6995055 | Structure of a semiconductor integrated circuit and method of manufacturing the same A method of fabricating CMOS transistors of first and second conductivity types in an SOI substrate includes the steps of etching contact holes and alignment marks through the semiconductor and insulating films and into the support substrate of an SOI substrate, for... | 02/07/2006 |
| 6984855 | Manufacturing method of semiconductor device and semiconductor device A semiconductor device comprising a buried insulating film formed in a substrate; a protective film formed on the buried insulating film covering corresponding diffusion regions of a P-type MISFET and a N-type MISFET, wherein the protective film is etch resistant to... | 01/10/2006 |
| 6982196 | Oxidation method for altering a film structure and CMOS transistor structure formed therewith A structure and method are provided in which a stress present in a film is reduced in magnitude by oxidizing the film through atomic oxygen supplied to a surface of the film. In an embodiment, a mask is used to selectively block portions of the film so that the stre... | 01/03/2006 |
| 6977195 | Test structure for characterizing junction leakage current For characterizing bulk leakage current of a junction, a center junction surrounded by an isolation structure is formed with a first depth. In addition, at least one periphery junction having a second depth greater than the first depth is formed in a portion of the ... | 12/20/2005 |
